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DSP Program and DSP Frequency for high sampling rates

Mario Huettel
Prodigy 10 points
Part Number: PCM5242

I want to use a PCM5242 DAC. For normal operation at various sample rates I want to use the default program 1 which is a interpolation filter that can be configured to allow x8/x4/x2/x1 oversampling for the DAC. According to table 7 (ROM Preset Programs) in the datasheet, the DSP needs 256 cycles for this filter per sample, which means, the DSP frequency has to be at least 256 times the sample frequency.

According to the datasheet, for 192 kHz a 2x oversampling is used internally (which means I need an interpolation filter).

The first line in the table shows this case. I understand where the prescalers for the OSRCLK and the DACCLK (NDAC and DOSR) come from. However, I don't understand, how the DSP frequency is calculated. The table lists a DSP Frequency of 24.576 MHz (=SCK), which is only 128 times the sampling frequency. So according to table 7 (see above), this is not enough to run the interpolation filter.

I know, that I can simply configure the PLL in the PCM5242 and generate a 256 times 192 kHz clock solely for the DSP which essentially is still in range of the clock spec. and would work as far as I see.

However, the datasheet explicitly lists the lower DSP frequency. How is this possible? Do I need to write a custom program for the DSP in that case? (Which I want to avoid because I simply want a DAC).

In 384 kHz Operation the case is similar. No matter how the device is clocked, the DSP will at most run at 49.152 MHz (128 times the sampling frequency) which is too low for the interpolation program. I'm aware, that I don't need an interpolation filter for 384 kHz operation, since the oversampling is x1. However, the DSP program cannot be disabled, as far as I see. A program is always active.

How to use the DAC with this sample frequency?

  • 0
    TI__Mastermind 30781 points

    Hello Mario,

    In software mode, when there is   valid bit SCK, BCK and LRCK , the device will configure the clock tree (Figure 68. PCM5242 Clock Distribution Tree)  and PLL ( 8.8.5 PLL Calculation)  to drive the miniDSP as required.

    Also for a given sampling freq and SCK,   Table 50 and 51 lists  the needed DSP  and the PLL coefficients for each case.

    Here is a sample script that you can see how to program the DAC 

    # PLLCK = CLKIN x R x (J.D) / P = 11.3MHz x 1 x 8 / 1 = 90.316 MHz
    # PLL clock source = SCK
    w E0 0D 00
    # P = 1
    w E0 14 00
    # J = 8
    w E0 15 08
    # Decimal value = 0
    # R = 0
    w E0 18 00

    #DSP CLK = PLLCLK/DDSP = 90.316 MHz /2 = 45.15 MHz
    # division by 2
    w E0 1B 01
    # DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
    # Division by 16
    w E0 1C 0F
    # CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
    # Division by 4
    w E0 1D 03
    # Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
    # Division by 8
    w E0 1E 07

    Hope that clears your question.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 10 points

    Hi Arash,

    thanks for the answer. Unfortunately this doesn't explain the behavior to me. I want to use the PCM5242 with SCK as the reference clock. Table 52 lists: 24.576 MHz SCK as reference clock for a 192 kHz operation. Effectively clocking the DSP at 24.576 MHz which is 128 times the sample frequency.

    Table 7, however, lists a minimum DSP cycle count for the interpolation filter of 256 cycles. I don't understand this. Is the cycle time inaccurate?

    Thanks

    Mario

  • 0 in reply to Mario Huettel
    TI__Mastermind 30781 points

    Hi Mario, 

    Ok, I see what you are asking, I doubt the cycle time is wrong, but let me go to data sheet and dig more about it.

    I  will answer you no later than Thursday. Thanks for your patience.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Mastermind 30781 points

    Hi Mario, I discussed it with other colleagues,  the opinions were it could have been  a simple typo. Thanks for your patience.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 10 points

    Hi Arash,

    thanks for the answer. It would be great if there was a way to actually get the actual number. But it is fine for now. I can start designing my architecture and clocking schemes.

    Thank you!

  • 0 in reply to Mario Huettel
    TI__Mastermind 30781 points

    Hi Mario,

    When I discussed it with colleagues  with DSP background, the opinion was the number of tabs could be selected by designer to be more, may be for implementation efficiency , also it could have been a typo and it should be 128.  Since the mentioned minimum cycle is 256, I still would design with 256,  to be on the safe side. Sorry that I can not give you more insight into this.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 10 points

     Since the mentioned minimum cycle is 256, I still would design with 256,  to be on the safe side

    Hi Arash, unfortunately, this is not possible. When operating at 384kHz, running the DSP at 256x is not possible, as this violates the spec for the maximum frequency. I have to use 128x. I guess I just have to move to another DAC with a non-conflicting datasheet to be safe..

  • 0 in reply to Mario Huettel
    TI__Mastermind 30781 points

    Hi Mario,

    It is a mature part  and  I could not find any more documentation for this , also I have not heard any question about the correctness of  that value . Sorry that  I can not offer more insight 

    Regards,

    Arash