Hi team,
According to Figure 37 on page 26 of the data sheet, the Sync pin of each IC is connected with 10 kΩ, and a 1 nF bypass capacitor is implemented on the Sync pin of the slave side.
However, if a 1nF bypass capacitor is implemented, the clock waveform of the Sync pin on the slave side is distorted, and synchronization with the master side cannot be obtained.
This problem can be solved by leaving the bypass capacitor unconnected.
The clock frequency of the IC is set to 600 kHz.
Is there any risk in leaving the bypass capacitor unconnected?
Sincerely,
Ryu.
