PCM3060: External reset operation

Hi,

DOUT should go high 2048/fs after internal reset, maybe it's so small that they are showing as though they are coming out at the same time.

Regards.

Hi,

Thanks for the reply.
Referring to Figure 23, it appears that RST, ADPSV, and DAPSV start up at the same time.
From Figure 22, I understood that the internal reset is activated after ADPSV and DAPSV are activated, but at this time, do ADPSV and DAPSV go down even if the RST pin is Low?
Or do ADPSV and DAPSV go Low as soon as RST goes High?

Sincerely,
Ryu.

Figure 22 is power on reset where VDD is ramping up, figure 23 is VDD is up, and external reset is applied.

Yes, the ADPSV/DAPSV goes down after VDD reaches the VDD typical even RST pin is low.

If RST is low, the internal reset will not be released.

Regards.

Hi,

Does this mean that the internal reset is released at the same time as the rising edge of the RST pin and VOUT is output 2048/fs later?

Sincerely,
Ryu.

Sorry. I was asking about DOUT, not VOUT.

Sincerely,
Ryu.

Thank you for your response.
I checked again and DOUT was output 3.3μs after the rising edge of RST.
Is there any possible cause?
Fs is 48kHz.

Sincerely,
Ryu.

Hi Yamashita-san,

Peter is out today and will follow up with you tomorrow, but I did want to add that since you're using external reset, you should be referring to figure 23, not 22. Also the paragraph you highlighted is for internal reset after a power on. Unless I misunderstand, your situation is an external reset applied well after the device has powered on. The paragraph for that timing is below:

How long is the RST pin being held low for and are the values of ADPSV and DAPSV being changed? 

Hi Jeff,

Referring to Figures 22 and 23, it was not clear.
It is stated that RST goes HIGH after a sufficient amount of time, but the internal reset does not go HIGH unless RST goes HIGH.
After the internal reset goes HIGH, DOUT should output 2048/fs, but it does so earlier.

Sincerely,
Ryu.

In Figure 22:

Internal Reset goes high 1024 SCLK after VDD is up above threshold.

In this case, RST is default high as it's an active low logic.

In Figure 23:

Internal Reset goes high 1024 SCLK after RST goes high.

Can you provide the timing diagram which you see the 3.3us either in POR or external Reset case?

Please show the respective signals as in figure 22 or 23 of the datasheet.

Regards.

Hi,

The phenomenon I am experiencing is for external resets.
I have attached the situation that is happening.
Can you see it here?
After RST is set to Low, there is a long time before it is set back to High.
I was expecting DOUT to start outputting 2048/fs after Internal Reset went High, but it started outputting 3.3μs after RST went High.
I would like to know why this is.

Sincerely,
Ryu.

How do you measure the 3.3us since only RST is a pin and ADPSV/DAPSV is a register?

As highlighted below, the VOUT and DOUT are controlled by register ADPSV/DAPSV and when resuming to normal operation from external reset, sequence in Figure 22 is performed. 

Since ADPSV and internal reset are internal signals, the closest signal you can use to estimate is the register write (I2C) when disabling ADPSV/DAPSV register and then use that to gauge the time to DOUT.

Hi,

For the RST pin rise and DOUT, the pins are measured directly with an oscilloscope.
As a result, as soon as the RST pin rises, BCLK and LRCLK start operating and DOUT starts outputting immediately.
I think it is strange because it means that Internal Reset never rises unless the RST pin is HIGH.
I am not controlling about ADPSV/DAPSV because I am operating in hardware mode.

Sincerely,
Ryu.

What's the MODE pin connected to?

In POR case, do you see the correct timing for hardware mode?

Once the above POR is correct and running, can you capture the following signal and trigger low on RST?

• VDD
• RST
• SCKI
• DOUT

Here I want to see the internal reset goes low which means DOUT should goes low.

Then after more than 2048/fs, set trigger to RST high and capture again.

Regards.

Hi,

The MODE pin is connected to VDD through 220 kΩ.
After RST is set low, DOUT is left high.
BCLK is low.
LRCLK is HIGH.
Each of them starts operating at the timing when RST goes HIGH.

Sincerely,
Ryu.

Hi Ryu,

Are you seeing the correct response during POR when VDD is ramping up?

Is DOUT low when powering up and then with data after VIN is provided and VDD is stable?

What you mentioned above does not seem to match the external reset diagram.

DOUT should go low after sometimes when RST is pulled low. Do you not see that?

We don't have EVM to verify and it will be good to check per figure 22 and 23 just to be sure.

Regards.

Hi,

We confirmed that when POR, the behavior is the same as in Figure 22.
After that, when an external reset is applied, DOUT and CLK begin to be output at the same time. (not as shown in Figure 23)
We do not have an EVM, only a circuit of our own making, so if possible, could you please confirm this with an EVM?

Sincerely,
Ryu.

Hi Yamashita-san,

Peter is out of office today. We will get back to you tomorrow about an EVM test.

Best regards,
Jeff McPherson

I'd expect to see DOUT to go low when EXT RST goes low. Are you seeing on all devices?

Can you provide the scope capture when external reset is applied as requested above?

I'd like to see RST, VIN, DOUT and CLK in the scope.

This is a legacy device, and we don't have EVM either.

Regards.

Hi

Attached is a captured image.
VDD is 3.3V all the way.

Sincerely,
Ryu.

DOUT never goes low when external reset is activated - it should go low after about 40ms.

Am I right the external reset is pulled low for more than 250ms?

This should be enough as it's more than 2048/48K~43ms. 

Are you seeing this on all devices, and anything connected to DOUT that might prevent it to go low?

Is DOUT coming up earlier an issue for your application?

Regards.

pdjuandi said:

Am I right the external reset is pulled low for more than 250ms?

What does this mean?
Does an external reset within 250ms after POR cause a problem?

I do not know if this is caused by DOUT occurring too quickly, but when the waveform becomes like this, white noise is generated.
Occasionally, DOUT operates as shown in Figure 23, in which case white noise is not generated.

Sincerely,
Ryu.

Hi Yamashita-san,

Peter is out of office this week so I will be taking over support. 

I believe what Peter was asking about comes from pg 16 of the data sheet: "The RST pin initiates external forced reset when RST is held LOW for at least tRST = 2048/fS" if the reset is not held for 2048/fs, unexpected behavior can occur and the device may not fully reset, resulting in the quick DOUT time you see. 

From the scope it's hard to tell how the long the reset last. I am concerned that the RST signal increases gradually. Without a clear edge, the timing is hard to verify and you may get unexpected results.

Best regards,
Jeff McPherson

Hi Jeff,

Thanks for the reply.
The 2048/fs wait for time to elapse is well followed.

Sincerely,
Ryu.

Hi Yamashita-san,

Following on Peter's earlier question, does DOUT ever go low if you continue to hold RST low? Also I am still concerned that since RST has no edge, the reset circuit may not be going off properly. All the timing diagrams in the datasheet show a clear edge on the RST signal.

Thank you,
Jeff McPherson

Hi Jeff,

Jeff McPherson said:

Following on Peter's earlier question, does DOUT ever go low if you continue to hold RST low?

It does not; it remains High even if the Low time of RST is extended.

Sincerely,
Ryu.

Hi Yamashita-san,

Can you show the scope plot of how external reset is initiated? The shot you shared earlier shows the RST from low to high, but can you share when RST goes high to low?

Thanks,
Jeff McPherson

Hi Jeff,

The waveform at the start of RST is attached.

Sincerely,
Ryu.

Hi Yamashita-san,

Thank you for the plot. Since DOUT is still high, I think there is an issue with the reset. Can the reset slew rate be increased? The slow decrease in the reset signal might be causing an incomplete reset sequence. The data sheet shows the reset signal should have a clear edge like BCLK and FSYNC do.

Best regards,
Jeff McPherson

Hi Jeff,

It is difficult to increase the speed any faster than the current speed of about 20 μs/V.
Is there an indicator of what speed would be acceptable?

Sincerely,
Ryu.

Hi Yamashita-san,

The reset slew rate should be comparable to the I2S clocks you have shown above. Something like 2-3V/us.

Best regards,
Jeff McPherson

Hi Jeff,

I understand.
Just can't go any faster in our environment.
Can you confirm that slowing down the RST signal in your environment will cause the same symptoms?

Sincerely,
Ryu

Hi Jeff,

I managed to increase the speed to about 6.5V/us, but the situation did not improve.
Is it still necessary to increase the speed up to 3V/us?
Are there any other possible factors?

Sincerely,
Ryu

Hi,

pdjuandi said:

At the moment, this RST pin is non-compliant, and we need to correct that.

What does this mean?
Also, it is difficult for the RST signal to be faster than 6.5V/µs.
Jeff said that it should be about 2~3V/µs, but does this mean it needs to be faster than BCLK?

Sincerely,
Ryu

Yamashita-San,

I was mistaken after looking at the plot again for RST pin. The scope is zoomed, it looks really slow at first glance.

In datasheet, it mentioned a Schmitt trigger input for RST so the input slope should have minimal impact.

Nonetheless, this is strange as the external reset does not seem to reset the DOUT. Can you see any changes in the VCC, VDD current?

The external reset will cause internal reset to go low and power down the part thus the current should show a drop.

Are you seeing this on all parts? Do you think you can force RST pin low with external equipment just to verify this is low enough to trigger the reset?

Regards.

Hi,

Thanks for the reply.
I will proceed to check.
If it is an internal reset, what other possible causes are there?
And if the internal reset is not working, what are the possible causes?
Also, there is no case that DOUT does not go Low when RST is applied, is there?

Sincerely,
Ryu

We know the POR reset case works, but in the external reset case it does not seem that RST pin causes the internal reset to trigger in your setup.

If the current does not change, that confirms reset never happens. Maybe there's no physical connection of RST pin to the DUT.

So, check the solder connection or try different unit etc.

Regards.

Hi,

The current was checked and found to be unchanged.
However, we checked with multiple devices with similar results.
Is there anything else I can think of besides having a bad connection?

Sincerely,
Ryu

So, it seems reset never happened. This is what we suspect that external reset never gets into the device.

Regards.

Sorry, I confirmed that there is no change in VCC and VDD is going down.
But even in that case, DOUT is not low.
Also, white noise is observed after recovery from external RST.
Is there any possible cause?

Sincerely,
Ryu

No, the VCC current did not drop, but the VDD current did.
By the way, is the reset operation different in master mode and slave mode?
Currently this error occurs when using in master mode, but when using in slave mode, the same process does not cause an error.

Sincerely,
Ryu

Ok, let me check internally if this applies to slave mode only.

Are you saying in slave mode, the DOUT is reset to zero when RST is pulled low?

Regards.

Yes, that is correct. No white noise is generated.

Sincerely,
Ryu

Is there any possible reason why this does not happen in slave mode?

Sincerely,
Ryu

We could not confirm as we don't have the board to verify. Can you use slave mode instead?