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TLV320ADC5140: TLV320ADC5140 and TLV320AIC3204 on the same bus with 1024 BCLKs/frame

caleb crome
Prodigy 10 points
Part Number: TLV320ADC5140
Other Parts Discussed in Thread: TLV320AIC3204

   I'm looking at using a TDM bus with 
  • 2 TLV320ADC5140 in digital PDM mode, for 16-channels 
  • 1 TLV320ADC5140 in analog mode, for 4 channels
  • 3 TLV320AIC3204, for another 6 channels
That's a total of 26 channels all together.  At 24-bits/sample, that would be a total of 624 BCLKs/frame if all on one pin. 
My thought is:  RUN the AIC3204's as channels 0-5.  They can have offsets set up to 255-24 bits, so the offsets seem like they should be okay.  
The 5140s appear to have up to 64 slots on the TDM bus, so can then come after the 3204s.  They'll start transmitting at bclk 144, and go well above the 3204's 256 bclk/frame.
So, the question is:  will there be any issues with the 3204 running the BCLK at 624 (or 1024 to keep it a power of 2) bclks/frame?  As long as i keep them assigned to slots that occupy bits lower than 256?
Conversely, I may run at 32bits/frame, which would mean 832 (or still 1024) bits/frame at least.
My frame speed would only be 32kHz though.  No need to go faster for this design.
Thanks, 
  -Caleb
  • 0
    TI__Mastermind 27820 points

    Hi Caleb,

    The largest MCLK/BLCK frequency this selection of ADC's and Codecs can input is 24.576MHz.This is limitation #1 for your use case. 

    That being said, theoretically there is no issue daisy-chaining these devices on a singular TDM bus for 26 channels. As long as you offset correctly between devices this should work fine.

    At 24 bits * 26channels * 32kHz fs. At minimum your BCLK must be at least 19.968MHz. However, ADC5140 has supported BCLK/FSYNC ratios for various sampling frequencies shown below. At 32kHz sampling, the max source clock frequency supported is 16.384MHz; limitation #2.

    As a solution I suggest providing a 24.576MHz source clock and sampling at 24kHz or 48kHz to reduce the likelihood of clock issues.

    24 bits also appears to be the largest word length supported for this many channels without exceeding 24.576MHz source clock.

    Regards,

  • 0 in reply to Daveon Douglas
    Prodigy 10 points

    Does this ratio apply no matter if we're using the PLL or not?

    Thanks,

     -Caleb

  • 0 in reply to caleb crome
    TI__Mastermind 27820 points

    Hi Caleb,

    Not entirely. However if you're using a non-standard source clock frequency, you will need to use the PLL in at least AIC3204 to generate the internal dsp clocks and lower jitter ASI clocks, I can double check for ADC5140. What is your MCLK/BCLK frequency?

    Regards,