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OPA1655: Additional insight on bypass/decoupling capacitance and power supply noise reduction

Camille Leclerc
Prodigy 100 points
Part Number: OPA1655
Other Parts Discussed in Thread: TINA-TI, , JFE150EVM

Hello team,

Using the OPA1655 under dual supply conditions (VS = ± 3V) to amplify a 10 kHz square wave modulated signal. The closed-loop bandwidth (or cutoff frequency) of the OPA1655 system I have designed is ~100 kHz. The simulated output noise density I simulated with TINA-TI and corroborated with hand calculations at 10 kHz is 3.73 μV/√Hz and I would like to try and keep it as close top this value as best as I can... which brings me to this discussion regarding power supply noise and bypass/decoupling capacitors.

I am using a B&K 1760A DC Power Supply which is rated to have a ≤1 mV rms ripple (assuming 20 MHz bandwidth as it is not specified in the datasheet attached). Neglecting 1/f flicker noise, the equivalent output noise density of this power supply would be 2.2 μV/√Hz broadband. I would like to reduce (or eliminate if possible) this power supply noise to be 3x lower than the 3.73 μV/√Hz from my OPA1655 output noise at 10 kHz. 

I plan on using 100 nF NP0/C0G package capacitor (for low ESR) as bypass capacitors and a 4 layer PCB with ground/power planes as suggested in Section 8.4.1 of the OPA1655 datasheet. 

If I want to further ensure good signal fidelity and reduce power supply noise should I:

1. Use additional low ESR ceramic and/or electrolytic caps in parallel to the 100 nF ones such that the equivalent low impedance if the capacitances  span the GBW of the OPA1655 or only the 100 kHz BW of the OPA1655 system I designed? (worried to use more capacitors due to possible resonances.) 

2. Use ferrite beads instead of additional bypass capacitors?

3. Is a capacitance multiplier circuit such as a emitter-follower NPN RC filter (referring to this video https://www.youtube.com/watch?v=wopmEyZKnYo) better to remove power supply noise compare to options 1. and 2. ?

Any other suggestions are welcomed and appreciated! 

Thanks for taking the time to read my post! (Apologies if any of these questions are mundane, it is my first time designing an analog circuit let alone a high precision/low noise one...) 

1760A_Series_datasheet.pdf

  • 0
    TI__Mastermind 22110 points

    Hey Camille, 

    You may consider adding an LC filter similar to what I did on my JFE150EVM. There is a much more detailed explanation in the video link below on power supply filtering. 

    https://www.ti.com/video/3872230260001

    The inductor value I used for my EVM below was 100uH. 

    Best Regards, 

    Chris Featherstone

  • 0 in reply to Chris Featherstone
    Prodigy 100 points

    Hi Chris,

    Thanks for replying!

    I watched the video you shared... but honestly, a whole lot of what Robert talked about went over my head. Robert essentially showed that to reduce incoming switching supply noise by >60 dB it is best to use a 2 stage LC circuit. 

    Referring to 

    Chris Featherstone said:
    You may consider adding an LC filter similar to what I did on my JFE150EVM

    Did you opt to use this type of filter for your power supply line since the capacitor can still be implemented as a bypass on the IC supply pins while the inductor and resistor in parallel provide additional noise attenuation? 

    From my limited understanding of bypass capacitor theory, I thought adding additional inductance to the supply traces is to be avoided. Or so long that the bypass cap is as close to IC supply pins as possible, any/additional inductance between the bypass cap and you power supply unit won't "hurt" the performance of the bypass cap?

    Appreciate your insight!

    Best,

    Cam

  • 0 in reply to Camille Leclerc
    TI__Mastermind 22110 points

    Hey Camille, 

    I am not a power supply expert however the inductor was used for filtering because at frequency inductors become an open and do not allow high frequency signals to be passed to the device. At DC inductors are shorts and allow the DC potential to be passed to the device. At frequency capacitors become shorts and short high frequency signals to ground. Capacitors are opens at DC. I added these footprints to my board because it was a discrete JFET solution that is sensitive to power supply noise. The OPA1655 has a power supply rejection ratio or PSRR specification associated with it. This combined with supply filtering should provide good performance. 

    The inductor L1 comes first in line with the power supply connection. You can see in my layout below that the capacitors come after the inductor. 

  • 0 in reply to Camille Leclerc
    TI__Mastermind 22110 points

    Hey Camille, 

    Here is the layout showing the inductor L1 right next to my power supply banana jack. Capacitor C1 and C2 come after the inductor to provide decoupling and a charge bucket so to speak to the devices. 

    Best Regards, 

    Chris Featherstone

  • 0 in reply to Chris Featherstone
    Prodigy 100 points

    Hey Chris,

    Thanks again for your continued insight and providing a layout PCB example!

    I'll run some calculations to ensure the frequency cutoff of the LC is is well below 1 kHz to try and prevent any power supply noise ≥ 10 kHz from reaching the op amp.

    Best,

    Cam

  • 0 in reply to Camille Leclerc
    TI__Mastermind 22110 points

    Hey Camille, 

    No problem. Let me know if I can be of further assistance. 

    Best Regards, 

    Chris Featherstone