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TLV320AIC3100: TLV320AIC3100

Bruce Doan
Prodigy 210 points

Part Number: TLV320AIC3100
Other Parts Discussed in Thread: TLV320AIC23B,

For a PCB layout that is only 4 layers, how do you suggest separating the Analog ground and Digital ground?

Is it really necessary to split the ground plane layer?

  • 0
    TI__Guru 51200 points

    Hi Bruce,

    It's recommended to keep Analog Ground and Digital Ground separate to prevent digital noise from coupling into the analog portions of the device. However it's a controversial design choice since it also runs the risk of creating loop inductance which opens a whole other set of issues.

    In this case the only tricky part is the DVSS pin since it lives on the other side of the device from the rest of the digital signals and ground plane. Otherwise very little current should flow between the analog and digital ground connections and the respective signal traces can all live above their respective planes. The current return paths will stay within their respective planes. As long as the DVSS path has some distance and does not overlap any analog signals or ground, it should be fine.

    In the interest of transparency, the EVM does not actually follow the datasheet advice. It uses a partition method: one very large ground plane (cross all layers), with care taken such that digital and analog signals do not overlap and that their return currents do not interfere with one another. In this case the DVSS pin is connected to the thermal pad.

    This note gives some good advice on grounding methods: https://www.ti.com/lit/an/slyt512/slyt512.pdf?ts=1715274647538&ref_url=https%253A%252F%252Fwww.google.com%252F

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 210 points

    The ground plane is layer 2 (below the top layer) and is a continuous plane with only vias interrupting it.

    I am hesitant to break up that ground plane.  Past layouts with the TLV320AIC23b have successfully used just that solid plane with all decoupling caps and device grounds going through vias directly to the ground plane layer.

    The current layout has problems and I see a -18db continuous output (at my DSP) from the ADC Dout.
    It is not audible and any real audio does get through, but this phantom signal needs to go.

    Do you have any suggestions on how to identify the cause?  I have not yet tried modifying the init code to leave the ADC muted or powered off.

    Also, the output from the ADC seems very "hot".
    I need to back my analog input very far down to prevent clipping.

    What is the analog "full scale" input level?

  • 0 in reply to Bruce Doan
    TI__Guru 51200 points

    Hi Bruce,

    A single ground plane is fine as long as analog signals and digital signals are portioned and do not cross each other. 

    -18dB is quite loud for an idle signal. It sounds like your gain is configured very high. You could also try muting the ADC and seeing if the interference is in the ADC path or if it's coupling from somewhere else. I'd also double check if your Class-D output switching is causing noise on the input path.

    Full scale is 0.707Vrms, same as the AIC32b.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 210 points

    We are revising the PCB layout to correct noise issues.

    Are ferrite beads needed in the supply lines for the TLV320AIC3100?

  • 0 in reply to Bruce Doan
    TI__Guru 51200 points

    Hi Bruce,

    We don't require ferrite beads in the supply. Typically only the switching supplies (SPKVDD) would really benefit from a ferrite bead filter, but you're welcome to use them on the other power supplies if you're concerned about noise coming from the supply.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 210 points

    One more power supply question. 
    I am currently using paralleled 10uf, 100nf, 10nf on some of my digital supplies. Is there really much advantage to having the 10uf (bulk filter) caps be 0805 size instead of 0603? Will using an 0603 with a higher voltage rating help offset the reduced capacitance value with applied voltage effect?  These are all 3.3v or lower rails. 

  • 0 in reply to Bruce Doan
    TI__Guru 51200 points

    Hi Bruce,

    Yes, a higher voltage would prevent the applied voltage effect from lowering the capacitance, however this benefit drops off dramatically once the cap has twice the rating of the highest intended supply voltage. For example the EVM uses 6.3V caps for 3.3V rails. You could use higher rated caps but there's not much benefit to do so. The trade off of space/cost required for 0805 caps doesn't justify the capacitance improvement in my opinion. 

    Best regards,
    Jeff McPherson