SRC4392: SRC Latency

Hello Stephan,

The latency in all SRC devices is mainly coming from decimation or interpolation filter and is a fixed number related to 1/fs - that is shown in datasheets as group delay.

There is no mechanism to modify  it internally 

Arash

Hi Arash,

thanks for your reply.

In the meantime, I have found out, that the varying latency (+/- ca. 10us) happens, when the soft mute function (bit 4 in reg. x2D) is being used.

If this bit is permanently set to zero, the latency seems to be constant between several chips on the same pcb.

Now we have several pcbs with several SRC4392 in a frame, and we still see a variation of the latency between these.

We can deactivate the SRCs and test with synchronous signals to confirm that this happens within the SRC4392.

The variation is in sub-sample range, which is another hint that it must be produced within the chip.

So there is probably a mechanism, which calculates / interpolates the filter coefficients, which is not only depending on the clocks of the incoming and outgoing signals, but which is also influenced by the timing of a reset or power-up process.

Would you possibly have some information on that?

Thanks and kind regards

Stephan

Hi Stephan,

the latency of SRC is solely depends on decimation or interpolation filters inside them,  which is fix and related to fs, however  the mute function forces the SRC output data low by stepping the output attenuation from the current setting to an all-zero data output state and it involves some logic gates. Also the reset sequence forces all registers and buffers to their default settings and from figure 60, it has a min 500us needed time.

Activation of the soft mute and reset occurrence have  variation from chip to chip which   is not uniform for an array of these devices, so I believe what is hitting you is not the actual latency, it is the  variation of internal reset function.

These are mature devices and the only documents that we have are what you see in the product page. 

You might want to consider latching the output data from individual SRCs  with the same clk to sync the outputs.

Regards,

Arash

Hi Arash,

the output data is latched with exactly the same clock signals.

The latency we measure must be caused by different filter coefficients (i. e. phase of polyphase filters), which apparently depend not only on the input and output clocks, but somehow also on the reset, and even on the activation of the SRC soft mute.

Just to confirm once more, it's not about the signals going out of mute at different times, but the actual audio signal does not have the same latency through each chip, although the clock signals and audio data going in are exactly the same.

Kind regards

Stephan

Hi Stephan,

Arash is out of office today and will follow up with you tomorrow.

Thanks for your patience,
Jeff McPherson

Hi Stephan,

Sorry, Arash will be back Wednesday.

Thanks for your patience,
Jeff McPherson

Hi Stephan,

As far as I know the main latency is coming from internal filters and it is fixed per Fs . Having said that, in any IC, there is a variation in performance and parameters for digital gates. My opinion is that engaging reset , mute and etc introduces a variation for  start or reset which is separate from propagation delay from input to output . So as i said before , it is about signal going out of mute or finishing the reset at slightly different times not difference in propagation delay from input to output.

Regards,

Arash

Hi Arash,

thank you very much for your time and effort to try to answer my questions.

Would there be a chance to put me in direct contact with a design engineer, who is really acquainted with the details of the implementation?

Kind regards

Stephan