Dear TI,
My hardware produce the following signals to a PCM5121 in I2C, slave mode:
* 32-bit Left Adjusted, two's complement L/R audio samples at 312.5kHz
* LRCK at 312.5kHz
* BCK at 20MHz (64*Fs)
* SCK at 40 MHz (128*Fs)
I have not been able to obtain a useful analog output in this mode, initially trying with the PLL off. Now, I suspect (the datasheet really is exceptionally poor - regretfully) that the internal detectors might be so closely tied to standard audio rates that the autoconf (PLL off) might not function at Fs = 312.5kHz - for this reason, I now try to configure the PLL...
In relation to this, It is not clear to me, from the datasheet, the required clock rates. Figure 62 says that the DACCK is 128Fs (my 40MHz SCK directly), but most examples from the datasheet seems not to go higher than around 6.144MHz for the DACCK; the objectives that need to be accomplished by the PLL setting is not clear to me by reading the datasheet.
Can you possibly help me either by directly giving me the objectives I need to fulfill in order to make it work at this rate? - alternatively point me towards some documentation that explains the required conditions related to the clocking/PLL setting in more detail?
Thank you and best regards
Morten
P.S: I am quite in a hurry; this is only a small part of a large design - and I had never anticipated such small detail to be such an obstacle