PCM5122: Big spark generated very rare and ramdomly by the PCM5122 also with costant 0 signal in the PCM_din.

Hello Francesco,

I can not see the details of the schematic due to its low resolution, would you please send the schematics in high resolution so it is readable.

Also can you elaborate on the spark, is it a load sound  (pop noise) or a real spark with a load sound. I assume a real spark  would damage the IC, so most probably it is just a loud pop noise, not a spark.

Since you mention the dividers are set correctly I assume you are using the DAC  in I2C configuration,  if so,   Dout doesn't exist in I2C configuration, it exists only in Hardware control (pin 16) . So do you mean  when there is no Dout at the  ADC , you still hear the pop noise ?

Few things to confirm or provide:

• Pull ADC input to ground so there is no code being send to the DAC and verify the issue persists.
• Disconnect the DAC from ADC's output  and feed the DAC with no input, this helps to confirm the cause might be due to  the supplies as you suspected.
• We need to have the scope plots for supplies, as well as all I2S signals going into the DAC. Pop noise usually is the result of clk halt/error as well as at power up and power down- when a capacitor at the output charges or discharges abruptly. it is important to capture the behavior of supply and I2S at the moment there is an issue so we can find the cause and possibly the root cause.

I put couple of links that you can refer to and might find it useful.

https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/1114638/faq-how-can-i-reduce-the-click-and-pop-noise-on-my-audio-switch-and-detection-jack

https://docs.kernel.org/sound/soc/pops-clicks.html

Regards,

Arash

Dear Arash,

thanks a lot for your prompt answer to my question, and sorry for my poor description of the application, now I give you all the detailed information about the design, file attached:

• “Digital audio” system description.
• Complete schematics diagram of the Raspberry CPU interface, see page #2 about the schematic of digital audio.
• Digital recording of the I2S signal from CM4 to the two DAC, from Logic Analyser, exactly when the pulse issue happened 2024-06-03_13-56-59.kvdat. Download the software to read the data from this site:

https://www.qdkingst.com/en/download

• Conversion of digital I2S signal in numerical data, file excel, from LA when spark issue happened, 2024-06-03_13-56-59.xlsx.
• Code example of the two PCM5122 configuration, PCM5122 code.cpp.

Download from here the file:

https://sendgb.com/TulGgnWCwZQ

The issue description:

Randomly, a big pulse is generated in the analog output of the DAC, randomly left or right channel, also the intensity of the pulse could be of different level.

In the loudspeaker seem like a shot or spark, is not an electrical spark, but the DAC continuing to work regularly, the sound is very good, it not seem to be damaged.

Only one DAC present this issue, is the U6 in the schematics, LRCK#1. In some way is related the forced bit data to generate LR_CK divided by two.

This pulse is not in the digital data of the I2S as showed by the excel file derived from the LA data, samples in the moment of the pulse.

I see the probability to have this random pulse is in some way proportional the noise in the board.

Reducing the noise of keyboard scanning reducing the pul_up resistors, fixing some floating input, or converting it to fixed output signal and other similar action has reduce a lot the probability to have the random pulse in the output.

Now the probability is one pulse in some hours.

In the DAC configuration automute is disabled, and also any other I2S signal error action are disabled.

I have also set the three pins GPIO3/4/5 from free input to fixed output.

Could be a solution changing the DAC Architecture with register 79hex from Hyper-Advanced to Classical?

Is more than a month I’m working on this issue without find the final solution.

Cloud you help me? Please this is a very urgent

Thank a lot.

 Francesco

Dear Arash,

the acquisition of I2S signal from the logic analyzer shown there are no interruption or discontinuity on these signal.

If you can't download the app to read the I2S signal please download some images of these here:

https://drive.google.com/file/d/1lXmJegfKpwzq3Xs7sAutIuBHZ0ZU4O1g/view?usp=sharing

https://drive.google.com/file/d/1lWFBfc500KVBrRUUFIUE5SfS427DAVAB/view?usp=sharing

https://drive.google.com/file/d/1lX-zVvK_VOxyKJWYe1qnkXkQk3IzCtik/view?usp=sharing

In all the test and improvement obtained the pop noise seem to be related to an high sensitivity of the DAC to the noise on the board or signal integrity.

Could you please have a look the schematic diagram and indicate me how to iporve integrity of the I2S signal with filter?

Download the schematics from this link:

 https://drive.google.com/file/d/1S5V-VSjqDMhaFVoHcVBUYvI5pDRks5xu/view?usp=drive_link 

The exchange of LRCK between DACs is a good test to do, I'll do it.

Could you better explain the tabbing from LRCK, this is not clear to me,

thanks a lot

Hello Francesco,

I can not open file sharing locations for security reasons as well. Probably it is not needed for me to look at the clks since I wanted to see the I2S signals right at the moment that there is a pop noise but again, since pop noise cause is well known in DACs, most probably you should be able to see an issue with the clks ( integrity or noise level) at that random moment. I don't think there is anything that you can do with the DAC itself rather you have to work on the signals getting into it. 

Exchanging of LRCLK b/w the 2 DAC was one suggestion and another suggestion was instead of swapping the DACs, send the same clk line that is working for a given DAC to the other DAC as well. may be add a buffer and tab both DACs from same clk line. Since it happens very randomly and not very often, it might be hard to find the source in your clk tree.

Regards,

Arash

Dear Arash,

I'll try with this suggestion to better understand the origin of the issue.

As for your experience, to reduce the probability of this pop noise is better to use external SCK as a master or use internal PLL to generate internal SCK from BCK as reference?

In the I2S interface the DIN data out of the 24bit word could be a source of the pop noise if this bits is randomly 0-1?

To reduce the probability of pop noise is better to disable any action on error on BCK, LRCK, SCK?

Disable auto-mute is better to reduce pop noise?

I'm using this sequence for setting the PCM5122 registers, with this code, could you verify if the sequence is correct?

Dear Arash,

after inverting the LRCK#1 with LRCK#2 going to DACs, the pop noise is moved from the first to the second DAC, also receiving the same data stream of original case. So it really seem to be related to the inverted output of the flip-flop, this is very unbelievable. But anyway I can use only the good one LRCK differencing the data stream to DAC with the bit delay. I'm testing this solution,

Regards

Francesco

Thanks for the update. As i suspected and based on my past experience the source has to be the clks which you confirmed.

Regards,

Arash

Dear Arash,

this seem to be a never ending story. Using for both DACs in parallel the same good LRCK#2 the pop noise is not present in DAC#2 but return in DAC#1, incredible!

There could be an interaction of internal PLL? Is possible to disable the internal PLL and using as master clock the external SCK @22.5792MHz?

I try this configuration but it doesn't works, could you suggest a sequence of command to setup this?

Francesco