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TLV320ADC5140: One master and multiple slaves

Dhanaraj Shanmugam
Prodigy 20 points

Part Number: TLV320ADC5140

Tool/software:

Hi,

We have two ADCs that are connected to a master. TI ADC MCLK is supplied by an external clock due to inaccurate samples received by the master when mclk is provided by the master. 4 channel inputs are connected to TI ADC. Two channel inputs are connected with PMIC ADC. 

TI ADC: 4 ch, Singed 16 bit

PMIC ADC: 2 ch, Singed 32 bit

Sample rate 96khz

How to fix the slot numbers and transfer the data from slave to master?

  • 0
    TI__Guru 51470 points

    Hi Dhanaraj,

    This method is not possible. If MCLK is being supplied to the TI ADC, that means that the ADC5140 will be self generating BCLK and FSYNC. This should be driving to the RV1126 making the RV1126 the slave device. Or if you want the TI ADC to be the slave you should remove the external crystal.

    I'm not sure I understand your question. The default word length for the ADC is 16 bits. To get 4 channels you should configure register 0x0B through 0x0E such that channels 1 through 4 occupy slots 1 through 4 respectively.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 20 points

    I have made the changes to the MCLK connection and I have verified the independent communication between RV1126 and TI ADC. I also have verified the communication between RV1126 and PMIC ADC. Now I want to connect both and I want RV1126 to receive the data from both. What is the recommended way to achieve this?

    My initial thought is to assign all data from one ADC to the left and another ADC data to the right. So together it'll be 4 16-bit data on the left and 2 32-bit data on the right. But I am not sure whether this is a feasible way.

  • 0 in reply to Dhanaraj Shanmugam
    TI__Guru 51470 points

    Hi Dhanaraj,

    In this case it is better to use a TDM format. This will appear like 8 channels of 16 bits being transmitted one after the other, but your receiver will have to understand that channels 5&6 and 7&8 need to be appended together to give the full 32 bit channel.

    Both ADCs will also need to set their data output to hi-z when they are not transmitting to avoid contention.

    Best regards,
    Jeff McPherson