TAS2505: Register settings for using TDM with channel selection for TAS2505

Part Number: TAS2505
Other Parts Discussed in Thread: TAS2781, TLV320AIC3120EVM-U,

Tool/software:

Hello,

It seems like the TDM mode is enabled by setting Audio Interface = DSP for register 27 (page 0) as per page 71 of the Application Reference Guide.

(https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1366311/tas2505-tas2505-tdm-clocks/5217488)

However when I initialise the codec, the hp output seems to mix all TDM inputs down and only works when data offset = 0 (and offset = 16 or 32 outputs nothing), while I want to be able to select the channel from 1 to 8 by using the Data offset setting (register 28 page 0).

Could you please advise which settings are required for TDM in order to select a channel using the data offset (16 bit audio)?

Here are my initialisation settings, adapted from the Application Reference Guide:

cfg_reg tas2505InitCfg[] = {
    {0x00, 0x00}, // Page switch to Page 0
    {0x01, 0x01}, // Assert Software reset (P0, R1, D0=1)
    {0x00, 0x01}, // Page Switch to Page 1
    {0x02, 0x00}, // LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
    {0x00, 0x00}, // Page switch to Page 0
    {0x04, 0x05}, // PLL_clkin = BCLK, codec_clkin = PLL_CLK, MCLK should be 11.2896MHz (P0, R4, D1-D0=03)
    {0x05, 0x11}, // Power up PLL, set P=1, R=1, (Page-0, Reg-5)
    {0x06, 0x04}, // Set J=4, (Page-0, Reg-6)
    {0x07, 0x00}, // D = 0000, D(13:8) = 0, (Page-0, Reg-7)
    {0x08, 0x00}, // D(7:0) = 0, (Page-0, Reg-8)
    {CFG_META_DELAY, 15}, // add delay of 15 ms for PLL to lock
    {0x0B, 0x84}, // DAC NDAC Powered up, NDAC=4 (P0, R11, D7=1, D6-D0=0000100)
    {0x0C, 0x82}, // DAC MDAC Powered up, MDAC=2 (P0, R12, D7=1, D6-D0=0000010)
    {0x0D, 0x00}, //  DAC OSR(9:0)-> DOSR=128 (P0, R12, D1-D0=00)
    {0x0E, 0x80}, // DAC OSR(9:0)-> DOSR=128 (P0, R13, D7-D0=10000000)
    {0x1B, 0x40}, // Codec Interface control Word length = 16bits, BCLK&WCLK inputs, DSP mode. (P0, R27, D7-D6=01, D5-D4=00, D3-D2=00)
    {0x1C, 0x00}, // Data slot offset 00 (P0, R28, D7-D0=0000)
    {0x3C, 0x02}, // Dac Instruction programming PRB #2 for Mono routing. Type interpolation (x8) and 3 programmable Biquads. (P0, R60, D4-D0=0010)
    {0x00, 0x00}, // Page switch to Page 0
    {0x3F, 0x90}, // DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00)
    {0x41, 0x00}, // DAC digital gain 0dB (P0, R65, D7-D0=00000000) BEN WAS 0x00 
    {0x40, 0x04}, // DAC volume not muted. (P0, R64, D3=0, D2=1)
    {0x00, 0x01}, // Page Switch to Page 1
    {0x01, 0x10}, // Master Reference Powered on (P1, R1, D4=1)
    {0x0A, 0x00}, // Output common mode for DAC set to 0.9V (default) (P1, R10)
    {0x0C, 0x04}, // Mixer P output is connected to HP Out Mixer (P1, R12, D2=1)
    {0x16, 0x00}, // HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)
    {0x18, 0x00}, // No need to enable Mixer M and Mixer P, AINL Voulme, 0dB Gain (P1, R24, D7=1, D6-D0=0000000)
    {0x09, 0x20}, // Power up HP (P1, R9, D5=1)
    {0x10, 0x00}, // Unmute HP with 0dB gain (P1, R16, D4=1)
    {0x2E, 0x00}, // SPK attn. Gain =0dB (P1, R46, D6-D0=000000)
    {0x30, 0x10}, // SPK driver Gain=6.0dB (P1, R48, D6-D4=001)
    {0x2D, 0x02} // SPK powered up (P1, R45, D1=1)
};

Thank you!

  • Hi Ben, 

    The engineer who normally supports this IC is on travel currently. please allow me one day to check this for you

    Regards,
    Arthur

  • Thanks Arthur I hope we can get this working asap.

    It would be amazing if you could provide the register config for what we are trying to achieve (we've used the TAS2781 before and it was much simpler), as I find the Clock/PLL related settings confusing. I've tried to play with the Audio_CODEC_ADC_PLL_Calculator.xlsx tool without success, and not sure if it's been updated for this codec.

    What we have is: TDM input with BCLK = 11.2896Mhz (we are not connecting MCLK), WCLK=44.1khz, and DIN gets the TDM data (8 channels of 16 bits). We are providing all the external power supplies.

    We want to output the channel of our choice (1 to 8) by using the data offset.

    Hope this is possible, we were told so before.

    Cheers, Ben

  • Hi Ben, 

    44.1kHz and 11.2896MHz and 8 channels gives 32 bits per channel, with 16 bit data.

    Since the input clock 11.2896 MHz is a multiple of the desired frame clock we do not need the PLL. it can be left powered off and CODEC_CLKIN can be the BCLK directly. NDAC=1, MDAC=2, DOSR=128. I discussed with the previously mentioned colleague who supports this and when it comes to calculating the PLL / divider values he will use the TLV320AIC3120EVM-U software in order to calculate these values

    Regards,

    Arthur

  • Thanks Arthur, that's very useful.

    However I believe the codec might not support selecting the channel from the TDM, could you please check with your colleague?

    And if that's the case, what is the point of the TDM, as the datasheet says it supports multichannel operations?

    Cheers

  • Hi Ben, 

    you will be able to select the playback channel through the offset in page 0 register 0x1C.

    Regards,
    Arthur

  • Hi Arthur, good news regarding the channel select there is some progress as it seems to work now.

    I'm getting 3 sine waves of different frequencies on channels 1,2,3 and manage to select each of them separately with the offset 0x1C.

    However there is a lot of noise (a mixture of white noise and tremolo) even thought the TDM signals (BCLK, WCLK and DIN) are very clean.

    I've gone through all the settings and updated the mixers to output to HP only.

    Please see below my registers config and schematics (tas hp output is connected to another codec as analog input).

    Thanks again for your advice.

    {0x00, 0x00}, // Page switch to Page 0
        {0x01, 0x01}, // Assert Software reset (P0, R1, D0=1)
        {0x00, 0x01}, // Page Switch to Page 1
        {0x02, 0x00}, // LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
        {0x00, 0x00}, // Page switch to Page 0
        {0x04, 0x01}, // codec_clkin = BCLK
        {0x05, 0x01}, // No PLL required
        {0x0B, 0x81}, // DAC NDAC Powered up, NDAC=1
        {0x0C, 0x82}, // DAC MDAC Powered up, MDAC=2
        {0x0D, 0x00}, //  DAC OSR(9:0)-> DOSR=128 (P0, R12, D1-D0=00) 
        {0x0E, 0x80}, // DAC OSR(9:0)-> DOSR=128 (P0, R13, D7-D0=10000000)
        {0x1B, 0x40}, // Codec Interface control Word length = 16bits, BCLK input, DSP mode (0x40 / i2s=0x00)
        {0x1C, 0x00}, // Data slot offset
        {0x3C, 0x02}, // Dac Instruction programming PRB #2 for Mono routing. Type interpolation (x8) and 3 programmable Biquads. (P0, R60, D4-D0=0010)
        {0x00, 0x00}, // Page switch to Page 0
        {0x3F, 0x90}, // DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00) BEN WAS 0x90
        {0x41, 0x00}, // DAC digital gain 0dB 
        {0x40, 0x04}, // DAC volume not muted. (P0, R64, D3=0, D2=1)
        {0x00, 0x01}, // Page Switch to Page 1
        {0x01, 0x10}, // Master Reference Powered on (P1, R1, D4=1)
        {0x0A, 0x00}, // Output common mode for DAC set to 0.9V (default) (P1, R10)
        {0x0C, 0x08}, // Mixers: No analog routing to SPK driver and HP drive, DAC output is routed directly to HP driver
        {0x16, 0x28}, // HP Volume, dB Gain -20db
        {0x18, 0x75}, // No need to enable Mixer M and Mixer P, AINL Voulme, 0dB Gain (P1, R24, D7=1, D6-D0=0000000)
        {0x09, 0x20}, // Power up HP (P1, R9, D5=1), AINR/L disabed
        {0x10, 0x00} // Unmute HP with 0dB gain

  • Hi Ben

    I checked with your configuration and I am not seeing any severe distortion, are you hearing this noise from the output of the TAS device? or is this on the output of the    PCM device?

    The below TDM settings where checked.

  • Hi Arthur,

    We checked with the output from the TAS and it's the same, we tested on several boards and they all have the same problem.

    If you have any other ideas please let us know.

    Thanks, Ben

  • Hi Ben, 

    OK understand, I will discuss with the team and see what may be the issue.

    I will get back to you later today or tomorrow. 

    Regards,
    Arthur

  • Thanks Arthur,

    Also would it be worth trying to remove the external power supply (from 1.8v AP61102Z6 regulator) to AVDD and DVDD and use the internal power instead?

  • Hi Ben, 

    good idea, we have actually had some issues with the LDO before. I will check it.

    Regards,
    Arthur

  • Hi Arthur, any news on this, we've tried everything and still getting tremolo on a sine wave, we're stuck at this point.

    If your team could check our settings again and confirm about the LDO that would be really helpful.

    Thanks

  • Hi Ben, 

    I set this up and check again witht he LDO supplying AVDD and DVDD but it did not have an impact, 

    I was able to illicit some strange distortion by changing the BCLK polarity from my TDM source.

    Can you comment on your BCLK polarity, Can you confirm that each data bit is being setup on the falling edge and clocked in on the rising edge of BCLK?

    in addition is your frame start on FSYNC having a falling edge on BCLK at the same time?

    Regards,

    Arthur

  • Hi Arthur,

    Unfortunately we are getting very frustrated with this issue!

    We purchased the EVM but realised that we cannot test with TDM as the microcontroller generates its own signals to play from the USB.

    Playing I2S works perfectly fine. We do not understand why multichannel TDM has issues and wonder if it's ever been tested?

    See 2 screenshots of the signal, first one BCLK/WCLK and second one BCLK/DATA (we only have 2 probes), as you can see WCLK and DATA rise as BCLK falls (and we've tried inverting BCLK polarity too, and also tried with offset of data =1 or 2 etc., and all the different combinations of those settings).

    Could you please let us know how you are able to test your end? Do you use a simulation or the actual hardware?

    Many thanks, we're going to have to give up in the end if you cannot help us.

  • Hi Ben, 

    I tested on the TAS2505EVM, but i cut the traces and added a 100 mil header to allow me to connect a TDM source. - so it was not simulated.

    When you are testing with I2S your BCLK frequency will be much lower in frequency correct? I am suspecting that when you are using the 11MHZ BCLK in DSP/TDM mode that the timings may be marginal or not meeting the requirements from the datasheet. 

    is it feasible for you to decrease the BCLK from 11.2896MHz to 5.6448MHz? if it is supported by your MCU you will still be able to achieve 8 channels of 16 bit data.

    Is it possible for you to take a capture of the waveform from the HP output and share it? it may give some clue at to what type of distortion we are having.

    Regards,
    Arthur

  • Hi Arthur,

    Yes you're right the I2S clock is around 2.82mhz.

    Unfortunately we have no control on the TDM source, so we won't be able to lower it down to 5.6mhz.

    I'm not too familiar with the timing requirements for the clocks, but it seems like this could be the issue indeed.

    However at 11.3mhz the BCLK period is around 88ns (and this can be seen from our screenshots), so 35ns should give plenty of time. Could this be an issue with the rise and fall time though, what happens if they're over 4ns?

    2 things to note:

    - Were you using a MCLK for your tests? As mentioned previously we only receive the BCLK

    - The previous codec we were using (TAS2781 which unfortunately we cannot use for this project) had no issues with the same TDM source, the timing requirements are similar though but with a lower tH and tL for BCLK (20ns) which could explain the difference:

    We took a couple of screenshots of the waveform from the hp output if this can help (original is a sine wave)

    and zoomed in:

    Thanks again for your help, much appreciated!

    Ben

  • Hi Ben, 

    yes i was using BLK with no MCLK input from my TDM source. also, same script as you with no modifications. 

    Is it possible for you to share the data that you are playing to the device? is it in a .wav file or data array or some other type?

    from the waveform you shared it looks similar to unsigned data being interpreted as signed two's complement.

    is the distortion that you are seeing like the second image? this waveform is constant?

    Regards,
    Arthur  

  • Hi Arthur,

    We are getting the TDM from a Teensy board, see https://www.pjrc.com/teensy/gui/?info=AudioOutputTDM.

    Regarding the waveform, not it is not stable, it fluctuates like you can see on the first image.

    Thank you, we are planning on doing more tests with the EVM by cutting the tracks like you did.

  • Hi Ben, 

    ok, interesting, one question, If you capture one frame of the FSYNC clock and the data signal, what does it look like? if you take this capture with persistence on. does the location of the data appear to be changing?

    in your case for the 256BCLKs per frame we would expect data to be toggling on first 16clks, and no toggling on the next 16, and so on. do you see such behavior?

    Regards,
    Arthur

  • Hi Arthur,

    Great news, in the end this was down to the TDM data not being correct.

    We were using the second TDM line (Teensy supports 2) and only checked the data was correct on the first one. There is a bug with TDM2 which meant that some random data was added to the TDM stream.

    We have now managed to get a perfect sound with inverting BCLK polarity and adding an offset of 1 bit.

    Thank you so much for your assistance and perseverance and time, we are very much relieved that the codec is working as expected!

    Apologies for not finding out about this issue sooner.

    Ben