Other Parts Discussed in Thread: TAS6424
Tool/software:
Hi team，
1、Are there any sequence and timing requirements for STANDBY, I2C initialization, MCLK, and the two clks of I2S?
2、If it is necessary to disconnect the I2S clock and re-apply the clock after normal operation, do we need to pull down sty and re-initialize?
Because the customer's MCLK and I2S CLK are not the same clock source, the current timing is as follows:
1. VDD power on
2. Provide MCLK
3. I2S CLK
4. Pull up STBY
5. Initialize
3、Test findings：
(1) When I2S bitclk and MCLK are not output at the same time, the audio interface of 6421 is in I2S format, and stby can only be placed after the two clks to avoid reporting a fault error. If it is placed before the two clks or between the two clks, a fault error will be reported. The value of register 0x11 is 0x16, and the value of register 0x13 is 0x32.
(2) When I2S bitclk and MCLK are output at the same time, the audio interface of 6421 is in TDM format, and then the bitclk and MCLK of I2S are connected together, at this time, stby is placed before the two clks, and a fault error is also reported. The status of the read register is the same as above. Only when stby is placed after clk will there be no error.
(3) Although the above two situations report errors, the sound is normal.
In addition, the customer tested 6424, and stby was placed before the two clks, but no fault error was reported.
Want to confirm whether the above is normal? Are the timing requirements of 6421 and 6424 different?
