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TAC5112-Q1: Is it possible to adjust the TDM format to sample on the rising edge of FSYNC?

Alan Xia
Genius 9910 points
Part Number: TAC5112-Q1
Other Parts Discussed in Thread: TAS6424, TAD5112, TAC5112

Tool/software:

Hi team，

The customer wants to use one TDM channel to supply TAS6424 and TAD5112. The TDM format configuration of TAS6424 is shown in the figure below:

However, the TDM format of TAD5112 does not match the format of 6421. I want to confirm whether 5112 can be configured to the same format as 6421 through registers?

From the current description of TAC5112 for TDM, it can be seen that TAC5112 supports the rising edge sampling transmission of FSYNC, which is different from the falling edge of TDM. I suggest that on DTAT, only a blank bit is inserted in the SLOT of 5112 to see if it can meet the requirements?

In addition, can you provide a script that can generate sound by default when inputting TDM data through GPI? I will ask the customer to compare his own script configuration.

  • 0
    TI__Mastermind 29765 points

    Hi,

    Set BCLK_POL=1 and offset 1 to match TAS6424.

    There's a preset configuration in the PPC3 or EVM user guide with default TDM format which you can use and set the above bit to match TAS6424.

    Regards.

  • 0 in reply to pdjuandi
    TI__Genius 9910 points

    Hi pdjuandi 

    The customer did not find the BCLK_POL=1 option in PPC3, is there more detailed guidance or is the customer's GUI incorrect?

    There is no BCLK_POL option in the page for configuring TDM format in PPC3

    1. So customers need to use registers to configure the specific TDM format?

    2. If using registers, can the following screenshot interface be written to the registers? Or is it read-only?

  • 0 in reply to Alan Xia
    TI__Mastermind 27710 points

    Hi Alan, 

    Invert the BCLK polarity and invert the data trasmit edge for both to be syncronous with the rising edge of bclk

    To see this view, click the advanced tab in the top right corner of the GUI