• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 30 subscribers
  • Views 315 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TAS5731M: Power-on sequence

Since Xiao
Prodigy 30 points
Part Number: TAS5731M


Tool/software:

Regarding the power-on timing of the 5731,
1. At present, our AVDD/DVDD(the two power supplies use the same) will be later than PVDD, but we can ensure that the two power supplies are stable, and then pull up PD and RST, may I ask in this case, AVDD/DVDD is later than PVDD, will there be a problem? (The specification requires AVDD/DVDD to be earlier than PVDD);
2. The specification requires that PD should be raised first, and then RST should be raised. At present, we have no spare GPIO to control RST, RST will be raised after powering on, PD will be later than RST, and 5731 will be initialized after PD is raised，would that be a problem?

  • 0
    TI__Intellectual 1870 points

    1. According to the datasheet, you must turn on AVDD/DVDD, delay 100us, and then turn on PVDD. (please see photo attached). However, the power supply sequencing can be flexible, especially for applications where AVDD/DVDD is generated from PVDD. There will be no problem if you power up PVDD first as long as /RESET and /PDN are kept low until both power supplies are stable.

    2. This may be a problem. The PD pin is essential for power down(initating the PWM stop sequence) while the RST pin is used to reset/ place the PWM in the
    hard-mute (high-impedance) state. Thus, the sequence described in the datasheet ensures that the device exits the power-down mode correctly before attempting to reset and initialize. If the RST is brought high before PD, the device might not initialize properly as it could still be in power down mode when the reset occurs. We recommend you to follow the specifications in the datasheet. To solve your problem you could try to use an RC delay circuit to ensure PD is brought high before RST, this is just a suggestion. Thanks.

    Regards,

    Sam

  • 0 in reply to Sam Yang
    Prodigy 30 points

    Hi Sam,thank you for your reply! Regarding the timing of PD and RST, if you mentioned that RST is pulled higher than PD first, the risk point is that the chip initialization may not be successful. So, if we test the chip initialization multiple times and there are no problems, can the timing of RST and PD not refer to the specifications?

  • 0 in reply to Since Xiao
    TI__Intellectual 1870 points

    Hi,

    If you test the chip initialization multiple times and there are no problems, this configuration may work in your case. However, we still recommend that you follow the power-up sequence provided in the datasheet. Thanks.

    Regards,

    Sam