Tool/software:
Hi Experts,
I am designing an audio amplifier application using the TPA3255.
I have a power supply that allows PVDD voltage adjustment during operation (like a Class-G supply).
Furthermore, I would like to implement PFFB to improve the noise/distortion performance of the amplifier.
The differential amplifier inputs would be driven directly by a DAC stage.
I have a few questions regarding this application.
- As far as I understand, since the TPA3255 is a closed-loop amplifier, its gain should be constant regardless of PVDD voltage (assuming there is no clipping).
Therefore, would it be okay to dynamically adjust the PVDD voltage during amplifier operation, or could this cause issues of any kind? - PFFB would be implemented according to SLAA788A, which specifies PVDD = 51 V for this amplifier. Does changing the PVDD voltage affect the PFFB design in any way, or are the given values valid for any PVDD voltage?
- SLAA788A includes an op-amp input stage for the PFFB implementation (apparently to limit the input bandwidth).
I would like to omit this stage, and instead directly connect the differential output stage of my DAC, which is also similarly bandwidth-limited.
However, the DAC output stage produces a common-mode DC offset of approx. 7 V. Would this DC offset (before the PFFB R_in resistor) cause any problems with PFFB?
Thank you very much in advance.
Regards,
Alexander Kharitonov