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TLV320DAC3101: Codec Reference Clock Needed in Slave Mode?

Jiahe Liu
Prodigy 110 points
Part Number: TLV320DAC3101

Tool/software:

Hello, when I was studying the example register setups for TLV320DAC3101 (section 6.3.10.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs on the TLV320DAC3101 datasheet), I noticed the PLL is powered up and that a reference clock source (e.g. MCLK) is needed as shown in the screenshot below. I was wondering if this is still required when TLV320DAC3101 operates in slave mode? From what I understand, the codec's clock is provided specifically for generating DAC_fs, but isn't DAC_fs equivalent to the WCLK that my master device already provided?

In addition, the master clock provided by my master device is 1.5238095MHz and WCLK is 16kHz. I was wondering if these values are ok. And could you please provide me with a script for the register settings to support these frequencies?

Thank you,

--Jiahe Liu 

  • 0
    TI__Intellectual 2280 points

    Hi Jiahe,

    The TLV320DAC3101 generates the DAC_fs internally based on the BCLK or MCLK given to the device, and yes it should be the same as the WCLK. Because of the way the device is designed, you still need the WCLK but the DAC_fs is used for the DAC internally. 

    The PLL is required if your MCLK to WCLK ratio is lower than 128, which is the default DOSR. In your case, the BCLK was around 96 times the WCLK, so you would need the PLL. You can find recommended PLL values in the CodecControl software which you can download here: https://www.ti.com/tool/TLV320DAC3101EVM-U (click on the SLAC366 download) and run a simulation of the TLV320DAC101EVM. Then, click on "Digital Audio Processing Serial Interface" and then "Internal Clock Gen Module" to get the digital configuration of the codec clock/PLL clock. You can input your sample rate and master/bit clock frequency, and then it will show you some recommended PLL parameters. You can use the I2C examples in the datasheet to lay out your I2C commands, but if you need more help with I2C specifics I can provide some code if you give me the parameters you end up using. 

    Let me know if you need help with the I2C for setting the PLL or if you have more questions.

    Best,
    Mir Jeffres

  • 0 in reply to Mir Jeffres
    Prodigy 110 points

    iHi Mir,

    Thank you for your reply! I read the TLV320DAC3101 datasheet and noticed that DOSR can be as big as 1024 by setting register 14 on page 0. Does that mean I don't need the PLL for the current clock frequencies I have?

    In addition, is there a minimum codec reference clock frequency required for TLV320DAC3101 to operate properly? I noticed the example script on the datasheet used a reference clock frequency (i.e. MCLK) of 11.2896 MHz, but the maximum frequency my master device can provide is 4MHz. I wonder if that is still ok.

    All the best,

    --Jiahe Liu

  • 0 in reply to Jiahe Liu
    TI__Mastermind 31690 points

    Hi Jiahe,

    The PLL is also required if your MCLK to WCLK ratio is not a power of 2. In your case your MCLK is a non integer relationship to 16kHz so you will need to use the PLL to make that MCLK work correctly. You can use this excel calculator to help you determine the correct values: https://www.ti.com/tool/download/SLAR163/01.00.00.00

    You can refer to the AIC3101 in the spreadsheet since the clock trees are the same, just ignore the ADC fs output.

    Best regards,
    Jeff McPherson