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PCM5102: PCM5102 vs UDA1334

Roberto Bizzarri
Prodigy 10 points
Part Number: PCM5102

Tool/software:

Hello, I'm an application engineer and I need some help to choose one of your DAC to replace an out of production NXP UDA1334 in an already existent FPGA based project.

The NXP UDA1334 is an hardware controlled DAC with internal PLL for a 3 wire LEFT JUSTIFIED digital audio data format interface at 24bit 96KHz driven with a BCK bitrate of 6.144MHz

I can't change the protocol already written in the main FPGA component of the device.

I've implemented in your PCM5102 DAC that, from the datasheet, is supposed to work and behave like the UDA1334 but without any success.

On paper they look almost identical (apart for an inverted mute logic) but something is missing because I can't manage to make it working.

Here is the UDA's pdf link.
www.nxp.com/.../UDA1334ATS.pdf

Any help would be greatly appreciated.

  • 0
    TI__Mastermind 22720 points

    Hi Roberto,

    I assume your schemaytics are correct and based on this assumption  I have the following comments.

    The relationship b/w fs and BCK is based on the following:

    BCK= # of Ch.  * Ch depth * fs  

    So for fs=96kHz ,  2 ch with 24Bit,   I calculated BCK has to be 4.608MHz.   which is different from your BCK.  A  BCK= 6.144MHz  is set for a 32Bit data, but if you send a 24bit data it will not work. 

    As fas as SCK (MCK) it has to comply with Table 3. System Master Clock Inputs for Audio Related Clocks  ( SCK is a fixed multiple of fs).

    Even when all clks are according to the mentioned requiement, the input data format needs to be checked as well, for example Figure 15. I 2S Audio Data Format shows the correct edges of clks and DIN for I2S format.  

    Let me know if you still have an issue after the above correction and modiications.

    Regards,

    Arash