Other Parts Discussed in Thread: SRC4382
Greetings,
With reference to SRC4382 datasheet SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
It is not clear from the description that the bits in the Rx status 2 register are masked by the Rx interrupt mask 1 register even for readback.
I spent quite some time trying to work out why the contents of the Rx status register 2 was always zero, no matter whether signal was valid or not. Normally I'd expect the interrupt mask to only affect interrupt generation from the status bits, not register readback. (I'm not using interrupts from this chip)
Consider this a request that the documentation be clarified. (but also, I'd consider this a chip erratum)
