PCM1794a

Also need to understand the DC offset and gain error/drift for this converter.

I posted these queries 2 days ago, but i see no response.

What is the response of the modulator?

Customer needs this and other info in order to go forward with his design.

Also need to understand the DC offset and gain error/drift for this converter.

Derek,

The current segment DAC operates at 64*192kHz=12.288MHz.

There are descriptions that "The lower 18 bits, associated with the MSB, are processed
by a five-level third-order delta-sigma modulator operated at 64 fS by default." in THEORY OF OPERATION section in the datasheet.

The DAC architecture is the current segment type so no intentional analog filter is equipped.  The analog filter should be realized by the external IV converter shown in TYPICAL CONNECTION DIAGRAM section in the datasheet.

For system clock rate the conditions in the ELECTRICAL CHARACTERISTICS section are recommended. (Fs=44.1kHz, SCK = 256fs)

Also for DC offset, it is specified as Bipolar zero error that it is +/-2% in the datasheet.  Gain error is specified +/-6% in the datasheet.

thanks patrick.

can you comment on the gain/offset drift over temperature?

can the gain/offset error be calibrated out at a particular temperature?

Sangram,

Unfortunately, we don't have the gain/offset drift data over temperature, and the device itself has no way to calibrate it out by itself at a particular temperature.

-d2