TLV320DAC3100EVM-U: tlv320aic31xx-codec 1-0018: aic31xx_setup_pll: Sample rate (48000) and format not supported!

Part Number: TLV320DAC3100EVM-U

Tool/software:

I am trying to test the TLV320DAC3100EVM-U kit with IMX93QS93 Linux board. I am able to detect it know as you can see here: 

root@qs93-5210:~# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: tlv320aic31xxco [tlv320aic31xx-codec], device 0: 443b0000.sai-tlv320dac31xx-hifi tlv320dac31xx-hifi-0 [443b0000.sai-tlv320dac31xx-hifi tlv320dac31xx-hifi-0]
  Subdevices: 1/1
  Subdevice #0: subdevice #0


and, 
 
root@qs93-5210:~# aplay -L
null
    Discard all samples (playback) or generate zero samples (capture)
sysdefault:CARD=tlv320aic31xxco
    tlv320aic31xx-codec, 443b0000.sai-tlv320dac31xx-hifi tlv320dac31xx-hifi-0
    Default Audio Device

- But when I tried to aplay sine wave I got the following errors: 

root@qs93-5210:~# speaker-test -D plughw:0,0 -c 2 -r 48000 -F S16_LE -t sine -f 500

speaker-test 1.2.8

Playback device is plughw:0,0
Stream parameters are 48000[  247.600154] tlv320aic31xx-codec 1-0018: aic31xx_setup_pll: Sample rate (48000) and format not supported
Hz, S16_LE, 2 ch[  247.610738] tlv320aic31xx-codec 1-0018: ASoC: error at snd_soc_dai_hw_params on tlv320dac31xx-hifi: -22
annels
Sine wave[  247.621511]  443b0000.sai-tlv320dac31xx-hifi: ASoC: error at __soc_pcm_hw_params on 443b0000.sai-tlv320dac31xx-hifi: -22
 rate is 500.0000Hz
Rate set to 48000Hz (requested 48000Hz)
Buffer size range from 32 to 131072
Period size range from 16 to 8184
Using max buffer size 131072
Periods = 4
Unable to set hw params for playback: Invalid argument
Setting of hwparams failed: Invalid argument


- I've seen this related kernel messages as well:
alsa-lib /usr/src/debug/alsa-lib/1.2.8-r0/src/ucm/main.c:1541:(snd_use_case_mgr_open) error: failed to import hw:0 use case configuration -2
No state is present for card tlv320aic31xxco
alsa-lib /usr/src/debug/alsa-lib/1.2.8-r0/src/ucm/main.c:1541:(snd_use_case_mgr_open) error: failed to import hw:0 use case configuration -2
Found hardware: "simple-card" "" "" "" ""
Hardware is initialized using a generic method


- Here it is my device tree : 
audio_clk: audio-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12288000>;
	};
	
	codec_audio: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "tlv320aic31xx-codec";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&codec_dai>;
		simple-audio-card,frame-master = <&codec_dai>;
		simple-audio-card,widgets =
    		"Microphone", "Mic Jack",
			"Line", "Line In",
			"Line", "Line Out",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Out";
		simple-audio-card,routing =
    		"Line In", "AIN1",      // Line input route
   			"Line Out", "HPL",      // Line out to left headphone
    		"Line Out", "HPR",      // Line out to right headphone
    		"Headphone Jack", "HPL",
    		"Headphone Jack", "HPR";
		status = "okay";
		cpu_dai: simple-audio-card,cpu {
			sound-dai = <&sai1>;
		};
		codec_dai: simple-audio-card,codec {
			sound-dai = <&audio_codec>;
			clocks = <&audio_clk>;
		};
	};
};

&sai1 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
	assigned-clocks = <&clk IMX93_CLK_SAI1>;
	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
	assigned-clock-rates = <12288000>; 
	clocks = <&clk IMX93_CLK_SAI1_IPG>, 
	<&clk IMX93_CLK_AUDIO_PLL>,
	<&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>, 
	<&clk IMX93_CLK_AUDIO_PLL>;
	clock-names = "bus", "mclk1", "mclk2", "mclk3", "pll";
};

&lpi2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	status = "okay";

	// Add TLV320AIC3100 audio codec node
	audio_codec: codec@18 {
		compatible = "ti,tlv320dac3100";
		pinctrl-names = "default";
		reg = <0x18>;
		#sound-dai-cells = <0>;
		reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
		HPVDD-supply = <&reg_vdd_3v3>; 
		AVDD-supply = <&reg_vdd_3v3>;
		DVDD-supply = <&reg_vref_1v8>;
		IOVDD-supply = <&reg_vdd_3v3>;
		SPRVDD-supply = <&reg_vdd_3v3>;
		SPLVDD-supply = <&reg_vdd_3v3>;
		status = "okay";
	};
};

I am struggling to make this work, could anyone help me out with this? 

  • Hi Ahmed,

    Our experts are on holiday today. They will follow up with you tomorrow.

    Thanks for your patience,
    Jeff McPherson

  • Hi Jeff, 

    Thank you for letting me know. 

    Ahmed

  • Hi Ahmed,

    Sure thing. They might need half a day or so to review your problem since it came in over the holiday but they will follow up with you soon.

    Thanks again,
    Jeff McPherson

  • Update:

    I modified my device tree like you can see here: 

    reg_audio_pwr_5v: regulator-audio-pwr_5v {
    		compatible = "regulator-fixed";
    		regulator-name = "audio-pwr_5v";
    		regulator-min-microvolt = <5000000>;
    		regulator-max-microvolt = <5000000>;
    		enable-active-high;
    		regulator-always-on;
    	};
    
    	reg_audio_pwr_3v3: regulator-audio-pwr_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "audio-pwr_3v3";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		enable-active-high;
    		regulator-always-on;
    	};
    
    	reg_audio_pwr_1v8: regulator-audio-pwr_1v8 {
    		compatible = "regulator-fixed";
    		regulator-name = "audio-pwr_1v8";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		enable-active-high;
    		regulator-always-on;
    	};
    
    	audio_clk: audio-clk {
    		compatible = "fixed-clock";
    		#clock-cells = <0>;
    		clock-frequency = <12288000>;
    	};
    	
    	codec_audio: sound {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "tlv320dac3100-codec";
    		simple-audio-card,format = "i2s";
    		simple-audio-card,bitclock-master = <&cpu_dai>;
    		simple-audio-card,frame-master = <&cpu_dai>;
    		simple-audio-card,widgets =
        		"Microphone", "Mic Jack",
    			"Line", "Line In",
    			"Line", "Line Out",
    			"Headphone", "Headphone Jack",
    			"Speaker", "Speaker Out";
    		simple-audio-card,routing =
    			"Mic Jack", "MICBIAS",
        		"Line In", "AIN1",      // Line input route
       			"Line Out", "HPL",      // Line out to left headphone
        		"Line Out", "HPR",      // Line out to right headphone
    			"Headphone Jack", "HPL",
        		"Headphone Jack", "HPR";
    		status = "okay";
    		cpu_dai: simple-audio-card,cpu {
    			sound-dai = <&sai1>;
    		};
    		codec_dai: simple-audio-card,codec {
    			sound-dai = <&audio_codec>;
    			clocks = <&audio_clk>;
    		};
    	};
    
    &sai1 {
    	#sound-dai-cells = <0>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&pinctrl_sai1>;
    	assigned-clocks = <&clk IMX93_CLK_SAI1>;
    	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
    	assigned-clock-rates = <12288000>;
    	fsl,sai-mclk-direction-output;
    	status = "okay";	
    };
    
    &lpi2c2 {
    	clock-frequency = <400000>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&pinctrl_lpi2c2>;
    	scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    	sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    	status = "okay";
    
    	// Add TLV320AIC3100 audio codec node
    	audio_codec: codec@18 {
    		compatible = "ti,tlv320dac3100";
    		pinctrl-names = "default";
    		reg = <0x18>;
    		#sound-dai-cells = <0>;
    		ai31xx-micbias-vg = <MICBIAS_2_5V>;
    		reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
    		HPVDD-supply = <&reg_audio_pwr_3v3>;
    		AVDD-supply = <&reg_audio_pwr_3v3>;
    		DVDD-supply = <&reg_audio_pwr_1v8>;
    		IOVDD-supply = <&reg_audio_pwr_3v3>;
    		SPRVDD-supply = <&reg_audio_pwr_3v3>;
    		SPLVDD-supply = <&reg_audio_pwr_3v3>;
    		SPKVDD-supply = <&reg_audio_pwr_5v>;
    	};
    };	


    And I am able to test the speaker just for Higher Sample Rates (441000Hz, 480000Hz).
    root@qs93-5210:~# speaker-test -D plughw:0,0 -r 441000 -F S16_LE -t sine -f 500 -c 2
    
    speaker-test 1.2.8
    
    Playback device is plughw:0,0
    Stream parameters are 441000Hz, S16_LE, 2 channels
    Sine wave rate is 500.0000Hz
    Rate set to 441000Hz (requested 441000Hz)
    Buffer size range from 73 to 301056
    Period size range from 36 to 18798
    Using max buffer size 301056
    Periods = 4
    was set period_size = 9408
    was set buffer_size = 301056
     0 - Front Left
     1 - Front Right
    ...


    But still not working for 48kHz Sample rate
    root@qs93-5210:~# speaker-test -D plughw:0,0 -r 48000 -F S16_LE -t sine -f 500 -c 2
    
    speaker-test 1.2.8
    
    Playback device is plughw:[   77.992689] tlv320aic31xx-codec 1-0018: aic31xx_setup_pll: Sample rate (48000) and format not supported
    0,0
    Stream param[   78.003218] tlv320aic31xx-codec 1-0018: ASoC: error at snd_soc_dai_hw_params on tlv320dac31xx-hifi: -22
    eters are 48000Hz[   78.014054]  443b0000.sai-tlv320dac31xx-hifi: ASoC: error at __soc_pcm_hw_params on 443b0000.sai-tlv320dac31xx-hifi: -22
    , S16_LE, 2 channels
    Sine wave rate is 500.0000Hz
    Rate set to 48000Hz (requested 48000Hz)
    Buffer size range from 32 to 131072
    Period size range from 16 to 8184
    Using max buffer size 131072
    Periods = 4
    Unable to set hw params for playback: Invalid argument
    Setting of hwparams failed: Invalid argument
    


    Any idea about the causes of this issue ??

  • Hi Ahmed,

    Can we get the following information:

    1) I2C dump of the device configuration registers in both functional case and the case where the device is not working?

    2) Can we monitor the I2S signals (BCLK, WCLK) for both the 480kHz and 48kHz recording commands on a scope?

    Thanks and Regards,

    Lakshmi Narasimhan

  • The codec is working now I changed the clock-frequency to 12000000 instead of 12288000

    audio_clk: audio-clk {
    		compatible = "fixed-clock";
    		#clock-cells = <0>;
    		clock-frequency = <12000000>;
    	};

    The TLV320AIC31XX.c Linux driver source code seems that mclk of 12288000 is not supported for 48kHz. 
    As you can see here : 

    	/* mclk/p    rate  pll: r  j     d     dosr ndac mdac  aors nadc madc */
    	/* 8k rate */
    	{  512000,   8000,	4, 48,   0,	128,  48,  2,   128,  48,  2},
    	{12000000,   8000,	1, 8, 1920,	128,  48,  2,	128,  48,  2},
    	{12000000,   8000,	1, 8, 1920,	128,  32,  3,	128,  32,  3},
    	{12500000,   8000,	1, 7, 8643,	128,  48,  2,	128,  48,  2},
    	/* 11.025k rate */
    	{  705600,  11025,	3, 48,   0,	128,  24,  3,	128,  24,  3},
    	{12000000,  11025,	1, 7, 5264,	128,  32,  2,	128,  32,  2},
    	{12000000,  11025,	1, 8, 4672,	128,  24,  3,	128,  24,  3},
    	{12500000,  11025,	1, 7, 2253,	128,  32,  2,	128,  32,  2},
    	/* 16k rate */
    	{  512000,  16000,	4, 48,   0,	128,  16,  3,	128,  16,  3},
    	{ 1024000,  16000,	2, 48,   0,	128,  16,  3,	128,  16,  3},
    	{12000000,  16000,	1, 8, 1920,	128,  24,  2,	128,  24,  2},
    	{12000000,  16000,	1, 8, 1920,	128,  16,  3,	128,  16,  3},
    	{12500000,  16000,	1, 7, 8643,	128,  24,  2,	128,  24,  2},
    	/* 22.05k rate */
    	{  705600,  22050,	4, 36,   0,	128,  12,  3,	128,  12,  3},
    	{ 1411200,  22050,	2, 36,   0,	128,  12,  3,	128,  12,  3},
    	{12000000,  22050,	1, 7, 5264,	128,  16,  2,	128,  16,  2},
    	{12000000,  22050,	1, 8, 4672,	128,  12,  3,	128,  12,  3},
    	{12500000,  22050,	1, 7, 2253,	128,  16,  2,	128,  16,  2},
    	/* 32k rate */
    	{ 1024000,  32000,      2, 48,   0,	128,  12,  2,	128,  12,  2},
    	{ 2048000,  32000,      1, 48,   0,	128,  12,  2,	128,  12,  2},
    	{12000000,  32000,	1, 8, 1920,	128,  12,  2,	128,  12,  2},
    	{12000000,  32000,	1, 8, 1920,	128,   8,  3,	128,   8,  3},
    	{12500000,  32000,	1, 7, 8643,	128,  12,  2,	128,  12,  2},
    	/* 44.1k rate */
    	{ 1411200,  44100,	2, 32,   0,	128,   8,  2,	128,   8,  2},
    	{ 2822400,  44100,	1, 32,   0,	128,   8,  2,	128,   8,  2},
    	{12000000,  44100,	1, 7, 5264,	128,   8,  2,	128,   8,  2},
    	{12000000,  44100,	1, 8, 4672,	128,   6,  3,	128,   6,  3},
    	{12500000,  44100,	1, 7, 2253,	128,   8,  2,	128,   8,  2},
    	/* 48k rate */
    	{ 1536000,  48000,	2, 32,   0,	128,   8,  2,	128,   8,  2},
    	{ 3072000,  48000,	1, 32,   0,	128,   8,  2,	128,   8,  2},
    	{12000000,  48000,	1, 8, 1920,	128,   8,  2,	128,   8,  2},
    	{12000000,  48000,	1, 7, 6800,	 96,   5,  4,	 96,   5,  4},
    	{12500000,  48000,	1, 7, 8643,	128,   8,  2,	128,   8,  2},
    	/* 88.2k rate */
    	{ 2822400,  88200,	2, 16,   0,	 64,   8,  2,	 64,   8,  2},
    	{ 5644800,  88200,	1, 16,   0,	 64,   8,  2,	 64,   8,  2},
    	{12000000,  88200,	1, 7, 5264,	 64,   8,  2,	 64,   8,  2},
    	{12000000,  88200,	1, 8, 4672,	 64,   6,  3,	 64,   6,  3},
    	{12500000,  88200,	1, 7, 2253,	 64,   8,  2,	 64,   8,  2},
    	/* 96k rate */
    	{ 3072000,  96000,	2, 16,   0,	 64,   8,  2,	 64,   8,  2},
    	{ 6144000,  96000,	1, 16,   0,	 64,   8,  2,	 64,   8,  2},
    	{12000000,  96000,	1, 8, 1920,	 64,   8,  2,	 64,   8,  2},
    	{12000000,  96000,	1, 7, 6800,	 48,   5,  4,	 48,   5,  4},
    	{12500000,  96000,	1, 7, 8643,	 64,   8,  2,	 64,   8,  2},
    	/* 176.4k rate */
    	{ 5644800, 176400,	2, 8,    0,	 32,   8,  2,	 32,   8,  2},
    	{11289600, 176400,	1, 8,    0,	 32,   8,  2,	 32,   8,  2},
    	{12000000, 176400,	1, 7, 5264,	 32,   8,  2,	 32,   8,  2},
    	{12000000, 176400,	1, 8, 4672,	 32,   6,  3,	 32,   6,  3},
    	{12500000, 176400,	1, 7, 2253,	 32,   8,  2,	 32,   8,  2},
    	/* 192k rate */
    	{ 6144000, 192000,	2, 8,	 0,	 32,   8,  2,	 32,   8,  2},
    	{12288000, 192000,	1, 8,	 0,	 32,   8,  2,	 32,   8,  2},
    	{12000000, 192000,	1, 8, 1920,	 32,   8,  2,	 32,   8,  2},
    	{12000000, 192000,	1, 7, 6800,	 24,   5,  4,	 24,   5,  4},
    	{12500000, 192000,	1, 7, 8643,	 32,   8,  2,	 32,   8,  2},
    };


    Still not sure if my approach is correct but it is working! 

  • Hi Ahmed,

    Good to know that it is now working.

    The above code lists the internal clock configurations for the device based on MCLK frequency and sampling rates. Since for 48kHz sampling rate the clock configurations are listed for 12MHz and not 12.288MHz, there was issue with 12.288MHz setting.

    Thanks and Regards,

    Lakshmi Narasimhan