PCM4202: Period of LRCK and BCK

Hi,

The sampling frequency must be a multiple of 44.1kHz or 48kHz and synchronous with the SCLK as supported SCLK:LRCLK ratio. SCK can't exceed 38.5MHz at Quad rate so the ratio required is 128fS. An example table shown below:

Hi Daveon,

Thank you for reply !

We thought that the sampling frequency listed in Table 1 were just Common examples, Is it incorrect ?
We would like to use the SCLK frequency of 27MHz, the BCLK frequency of 13.5MHz, and the LRCK frequency of 210.9kHz, Is this frequency setting not possible ?

We design ciruit so that SCK, BCLK, and LRCK are in a synchronous relationship.

Regarding SCLK, We set it to 27MHz from the following specification in the datasheet.

Regarding LRCLK, We set it to 210.9kHz from the following description & specification in the datasheet.
LRCLK is generated by dividing SCLK by 128.

Regarding BCLK, We set it to 13.5MHz from the following description in the datasheet.
BCLK is generated by multiplying LRCLK by 64.

Hi,

Unfortunately, PCM4202 will not be able to support that combination of ASI clock frequencies. This is due to PCM4202 being a hardware controlled ADC without an integrated PLL which would allow flexibility in the range of clock ratios and internal dividers supported.

Each SCK frequency rate/range have their own minimum and maximum limitations due to this limitation. The range given is to cover the multiples of 44.1k or 48kHz sampling.

If you're still in the preliminary design phase and the application requires 210kHz sampling I would recommend a later generation IC such as TAA5212 or TLV320ADC5120 , it is software controlled but will give you the needed flexibility in clock sourcing.

Hi Daveon,

Thank you for reply and proposal !

We have additional questions.

Are the clock frequencies settings listed in Table 1 for PCM Master Mode or DSD Output Mode?
Comparing the contents of Table 1 and Table 2 & Table 4, it seems that they match.

We want to use PCM4202 as PCM Slave Mode (Quad Rate) and have to Input the Sampling Clock(LRCK).
In this case as well, does the Sampling Clock(LRCK) frequency have to be a multiple of 44.1kHz or 48kHz?
And then, What frequency should the input system clock(SCKI) be set to?

When We refer to Table 3, there was a description of "with Clock Auto-Detection",
so We couldn't figure out what value to consider for fSCKI.

Hi,

Table 1 is only providing an example of common system clock and sampling rate frequencies given device limitations, it is applicable to both master and slave mode.

If you want to use Quad rate, the SCKI has to be 128*Fs or 192*Fs

For example:

BCLK = 2 * 24bit word length * 192kHz = 9.216MHz

LRCLK = 192kHz

SCLK = 128 * 192kHz = 24.576MHz

Hi Daveon,

Thank you for reply !

We have additional questions.

When We use PCM4202 as PCM Slave Mode (Quad Rate), how do we select 128*Fs or 192*Fs ?

When We use PCM4202 as PCM Slave Mode (Quad Rate) and input the Sampling Clock (LRCK) to the PCM4202, does the frequency of the Sampling Clock (LRCK) have to be a multiple of 44.1kHz or 48kHz as listed in Table 1?

Hi

PCM4202 is a hardware controlled device so you give logic, high or low, to the mode selections pins (FS0,FS1,FS2,FMT0, etc) to configure the device.

user6004480 said:

When We use PCM4202 as PCM Slave Mode (Quad Rate) and input the Sampling Clock (LRCK) to the PCM4202, does the frequency of the Sampling Clock (LRCK) have to be a multiple of 44.1kHz or 48kHz as listed in Table 1?

Yes

Hi Daveon,

Thank you for reply !
We have additional questions.

We are referring to the mode selections pins settings in Table3 and Table5 of the Datasheet,
There seems to be no option of 128*Fs or 192*Fs in PCM Slave Mode (Quad Rate).
Is it not possible to select 128*Fs or 192*Fs in PCM Slave Mode (Quad Rate)?

And just to be sure, We would like to know, in the end, does this mean that the PCM4202 cannot be operated at a sampling frequency of 216kHz (which is described as the maximum value in the datasheet)?
216kHz is not a multiple of 48kHz or 44.1kHz.

Hi,

There is no need to select the system clock frequency ratio. This is done automatically with auto clock detection.

You're correct, 216kHz sampling is not a multiple of 48kHz. The device will support the ratio 128*fs here: 

SCK = 128 * 216kHz = 27.648 MHz

BCLK = 2 * 24* 216kHz = 10.368MHz.

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Reverting back to your original ask: Can the device support a sampling frequency of 210.9kHz?

Both SCK and BCLK values (26.99MHz & 10.368MHz) at 128Fs are within the supported range outlined within the device. So I want to correct my original response of stating that is must be a multiple of 48kHz or 44.1kHz. Those are only common audio sampling rates.

However, 210.9kHz is still a non-standard audio sample rate, and while performance degradation is likely to be minimal or none, I suggest experimental validation or simulations to see how the system performs in this non-standard condition.

It is not clearly stated in the datasheet what is fully supported and what is not and I apologize for the confusion.

Hi Daveon,

Thank you for confirmation and detailed explanation!
Most of our questions has been clarified.

We have one last question.

Calculating from tLRCKP in Figure 6, the upper limit of Sampling Clock (LRCK)  can be read as 200kHz(=1/5us),
however is it correct to think that the upper limit of Sampling Clock of PCM4202 is 216kHz?

Hi, 

The tLRCLK does not represent the limit of sampling frequency supported but illustrates timing for typical use cases. PCM4202 should still support 216kHz as stated in Quad rate mode specifications.