SRC4190-Q1: Sample-rate Conversion Behavior Inquiry

Part Number: SRC4190-Q1

Tool/software:

Hi team,

Could you please address the SRC4190-Q1 question below?

In case the system #1 and #2 are independently working:

  • IN_CK1 and IN_CK2's frequency and phase are both synchronized. However, the phase has a slight difference and jitter.
  • OUT_CK1 and OUT_CK2's frequency and phase are both synchronized. However, the phase has a slight difference and jitter.
  • The serial signal #1 and #2 have same data and phase. However, the phase has a slight difference and jitter.
  • The serial signal #1 and IN_CLK1 are synchronized.
  • The serial signal #2 and IN_CLK2 are synchronized.

Will the rate converted data of serial signal #1 and sierial signal #2 same data?

Best regards,

Kazuki Itoh

  • Hello, if you feed the same data with the same clks to both devices, the output would be the same with some expected phase shift.

    Regards,

    Arash

  • Hi Arash-san,

    I have an additional question from the customer.

    The data and clock is roughly same, but the data generation and clock extraction is done by different device, so several ns phase shift/fluctionation is expected. 

    Would the output be still same in the above case as well?

    Also, "some expected phase shift" you mentioned is coming from the propagation delay and it doesn't impact that much, so it won't be shifted by 1 clock?

    Best  regards,

    Kazuki Itoh

  • Hello,

    Since the extraction  is done by different devices, then it all depends how matched they are. As you mentioned, I would expect some ns phase shift to be resulted. This difference might be ok with the devices or applications  that are receiving the final data/clks. 

    The phase shift that I mentioned can come from propagation delay and I don't expect to be like by one clk.

    Regards,

    Arash