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PCM6140-Q1: VREF, Gain, and DRE Questions

William Hachfeld
Prodigy 20 points
Part Number: PCM6140-Q1

Tool/software:

I'm prototyping a design connecting a single PCM6140-Q1 to a Raspberry Pi Zero 2W in order to convert the output of currently one, but eventually four, analog MEMS microphones. Specifically we are utilizing the TDK InvenSense ICS-40300 for its extended low frequency response (6 Hz to 20 kHz). Right now the prototype is on a breadboard (I'm using a VQFN to DIP adapter) so I'm not expecting low noise. Obviously the design will eventually be moved to a PCB. I've largely followed the reference design from Section 9.2.1 of the data sheet. Here are some specific notes:

  • The ICS-40300 is single-ended, and we are expecting to locate the 4 microphones directly on the board, so I'm utilizing single-ended AC coupling (CH1_INTYP = 0d, CH1_DC = 0d, CH1_INSRC = 1d). Instead of the 1 uF capacitors in the reference design, however, I'm using 22 uF capacitors with the 2.5 kOhm impedance setting (CH1_IMP = 0d) for an Fc of ~2.9 Hz. I've adjusted the quick-charge duration for the AC coupling capacitors to 50 ms (INCAP_QCHG = 3d). And I have a 22 uF coupling capacitor both between INP1 and the ICS-40300 output, and between INM and ground.
  • I'm utilizing the 3.3 V supply from the RPi for both IOVDD and AVDD. And I've enabled (AREG_SELECT = 1d) the on-chip regulator to generate the 1.8 V AREG. The AREG pin is coupled to ground via a 10 uF and 0.1 uF capacitor as shown in the reference design.
  • I am using MICBIAS to power the ICS-40300 as shown in the reference design (including the shown capacitors) with it set to AVDD (MBIAS_VAL = 6d). The ICS-40300 is capable of running off of either 1.8 V or 3.3 V.
  • I currently have VREF set to 1.375 V (ADC_FSCALE = 2d). More about that in a minute...
  • I currently have both DRE and AGC disabled (CH1_DREEN = 0d) and I'm manually setting the PGA gain (CH1_GAIN = ...). More about that in a minute as well... 
  • I have SHDNZ connected to GPIO24 of the RPi, along with a 4.7 kOhm resistor connecting it to ground to pull it low by default.

At the moment I'm not using either of the TI specific device drivers. I'm using Python to manually control SHDNZ and configure the PCM6140-Q1 via the I2C interface. And I've added a device tree overlay on the RPi to use the simple audio card driver to interface with the PCM6140-Q1 using I2S with the RPi currently as the master.

With all of this in place I am able to power up the codec, see it appear on the I2C bus from the RPi, configure the codec as outlined above, and successfully record one channel, 32-bit, 48 kHz sound from the codec using the Linux ALSA "arecord" command. However I ended up bumping the PGA gain all the way up to 42 dB in order to get semi-reasonable volume in the recording. The recording environment in this case simply being my home office with a HomePod playing some music at reasonable volume levels about 10 feet away from the microphone.

This seemed like way more gain than I should need - and resulted in a fairly noisy recording (although there is that breadboard factor too). This led me to do some additional searches and I found SBBA583 ("Working With Analog Inputs in the TLV320ADCX120 and PCMX120-Q1 Family") which further led me to the following questions:

  • The ICS-40300, as I understand it from the data sheet, has an output of 0.8 V +/- 0.355 Vrms. Consequently I'm currently attempting to set VREF to 1.375 V, which seemed like the best match based on Table 7-11 of the data sheet. But I guess I missed the "AVDD Range Requirement" column, which indicates that AVDD should be between 1.7 V and 1.9 V (i.e. 1.8 V nominal).
    • Am I correct in understanding that the codec will not function properly with ADC_FSCALE = 2d and AVDD of 3.3 V?
    • If so, what does the codec do in this case?
    • If so, the codec clearly has an on-board 1.8 V regulator, why does it need AVDD of 1.8 V if it can generate the 1.8 V internally?
  • SBBA583 clearly indicates that the best performance will be achieved for differential analog inputs by enabling DRE. Given Table 2-10 ("SNR Data") from that document is it safe to assume that DRE should also be enabled for single-ended analog inputs as well?

I guess the bottom line is that am looking for a little additional advice as to how to achieve the best performance from the codec. It seems like I need to add an external 1.8 V regulator to my design so I can provide 1.8 V AVDD/AREG, and not use the internal regulator, in order to best match the ICS-40300 output to the PCM6140-Q1's ADC inputs. Is that a correct assessment?

Thank you in advance for any advice you can provide on the above!

  • 0
    TI__Mastermind 27290 points

    Hi William, 

    The AVDD is partially used to provide input signal headroom and derive the voltage common mode of the ADC input. 1 Vrms single-ended signal is supported with 3.3V supply, this is where you will get the best performance.

  • 0 in reply to Daveon Douglas
    Prodigy 20 points

    Hi Daveon,

    Thank you for the quick response.

    My understanding from your reply, then, is the hardware design I've shown above should be fine (other than moving to a PCB), that I should switch VREF to 2.75 (ADC_FSCALE = 0d), and then either use AGC, DRE, or a fixed PGA gain to amplify the microphone's signal to better match the ADC's full range. Correct?

    My further understanding is the singled-ended, AC coupled, microphone signal will be applied to a VREF / 2 (1.375 V with ADC_FSCALE = 0d) DC bias by the codec prior to the ADC. So the 0.355 Vrms (max) signal from the microphone, without any DRE, AGC, or fixed PGA gain, would be in the range [0.875, 1.875] V. And with VREF at 2.75 V, I'd only be using about 36% of the ADC's full range. Consequently if I'm using a fixed PGA gain, I should apply about 8 dB gain (CH1_GAIN = 8d) for a ~2.512 voltage gain which should increase the range of the microphone signal to [0.119, 2.631] V. About 91% of the ADC's full range. Or, alternatively, use DRE or AGC to dynamically adjust the signal - especially in cases where the audio being recorded is especially quiet or has a high dynamic volume range.

    Does that all seem about right?

  • 0 in reply to William Hachfeld
    TI__Mastermind 27290 points

    Hi William,

    That is correct mostly,..

    2Vrms differential swing means each leg or input pin has a 1Vrms swing of opposite polarity, i.e 1.41V peak amplitude. Single-ended configuration is one pin, with 1vrms full scale range 

     The ADC charges the coupling capacitor to a common mode voltage of roughly 1.65V (3.3V/2) allowing sufficient headroom for a 1.414Vpeak signal without any clipping and audio distortion.

    Your methodology for using the PGA and AGC are correct. A disclaimer: when you use the PGA  you amplify the input signal but also ampligy the noise. Configuring the input capacitor for a physical high pass filter, as well as the integrated high-pass filter can help mitigate some low frequency noise.

    You can use the AGC to fine tune the desired output of the audio signal in small signal applications like you explained.

  • 0 in reply to Daveon Douglas
    Prodigy 20 points

    Thanks Daveon,

    I'm still a bit confused that the DC bias of the input signal ends up as AVDD / 2 rather than VREF / 2, based on section 2.2 (and in particular figure 2-3 of) SBAA583. But I will go with your number since you certainly know these parts far better than I do.

    I'll also take your disclaimer about the PGA gain into consideration. We are hoping to be able to process some of the infrasound picked up by the microphone. Hence the reason we are using the ICS-40300 and its 6 Hz low end frequency. And also why I've used the 22 uF AC coupling capacitors paired with the 2.5 kOhm input impedance setting for a physical high pass filter of Fc ~= 2.9 Hz. Right now I'm using HPF_SEL = 0d and have left the IIR coefficients at their default values for an all-pass filter. But this is only because the other 3 settings of HPF_SEL all lead to cutoff frequencies that are above the 6 Hz low end of the microphone (except at the low 16 kHz sample rate). I.e. they would throw away potentially usable signal. And I haven't yet broken out my Signals & Systems text book to refresh my memory on how to calculate appropriate transfer function coefficients to give a high-pass filter closer to 6 Hz.

    I've found SBAA400 and SBA401 after a bit of searching (the links from the data sheet are broken). I'll read those before determining whether our application is best suited to use a fixed gain for the PGA, the DRE, or the AGC.