PCMD3140EVM-PDK: Adding PCMD3140/TLV320ADCx140 to Jetson Xavier AGX Industrial via I2S

Hi,

It seems like you are not getting far through the device tree because there is an I2C connection issue. This is likely due to something else in your Linux device. Unfortunately, we do not have a Linux expert on the team so I am not sure that we can help more. Sorry about this.

Hi,

Thanks for the answer,if there is someone who know about the driver and what the following line means we would like to get some help.

We have tried to modify our device tree until we have encounter a different problem, and after adding some prints to your driver we have concluded that the problem is in the following line, and we don't know how to fix it, or how to change our device tree so the driver will upload completely

Device tree:

// SPDX-License-Identifier: GPL-2.0-only
/*
 * T194 p2822-0000 audio common DTSI file.
 *
 * Copyright (c) 2017-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 *
 */

#include <audio/tegra-platforms-audio-dai-links.dtsi>
#include <audio/tegra186-audio-dai-links.dtsi>
#include <audio/tegra186-audio-graph.dtsi>
#include <dt-bindings/gpio/tegra194-gpio.h>
#include <dt-bindings/audio/tegra194-audio.h>
#include <audio/tegra-platforms-audio-dmic3-5-switch.dtsi>

/ {

	aconnect@2a41000 {
		status = "okay";

		agic-controller@2a41000 {
			status = "okay";
		};

		adsp@2993000 {
			status = "okay";
		};
	};

	i2c@c250000 {
		rt5658: rt5659.7-001a@1a {
			compatible = "realtek,rt5658";
			reg = <0x1a>;

			/* refer include/sound/rt5659.h for the values to be used */
			realtek,jd-src = <2>; /* RT5659_JD_HDA_HEADER */
			realtek,dmic1-data-pin = <0>; /* RT5659_DMIC1_NULL */
			realtek,dmic2-data-pin = <0>; /* RT5659_DMIC2_NULL */

			/* Codec IRQ output */
			interrupt-parent = <&tegra_main_gpio>;
			interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
			clock-names = "mclk";

			#sound-dai-cells = <1>;

			sound-name-prefix = "CVB-RT";

			status = "okay";

			port {
				rt5658_ep: endpoint {
					remote-endpoint = <&i2s1_dap_ep>;
					mclk-fs = <256>;
					link-name = "rt565x-playback";
				};
			};
		};
	};

	// our Sound settings
	
//	&hdr40_i2c0 {
	i2c@c240000 {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";

        tlvcodec: tlvcodec@4e {
            compatible = "ti,tlv320adc3140";
            reg = <0x4e>;
            	#sound-dai-cells = <0>;

            ti,mic-bias-source = <6>;
            ti,pdm-edge-select = <0 1 0 1>;
            ti,gpi-config = <4 5 6 7>;
            ti,gpio-config = <0 0>;
            ti,gpo-config-1 = <0 0>;
            //ti,vref-source = <2>;
            //reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
            
            	status = "okay";
            	sound-name-prefix = "H40-TLV";
            	
            	port {
			tlv_ep: endpoint {
				remote-endpoint = <&hdr40_snd_i2s_dap_ep>;
				link-name = "tlv-4-mic-array";
			};
		};
            	
        };
    };

	/* Default for all I2S is long fsync width(31) */
	aconnect@2a41000 {
		ahub {
			/* I2S4 in Short frame sync for BT SCO */
			i2s@2901300 {
				bclk-ratio = <4>;
			};
		};
	};

	tegra_acsl_audio: acsl_audio {
		status = "okay";
	};

	hda@3510000 {
		status = "okay";

		nvidia,model = "NVIDIA Jetson AGX Xavier HDA";
	};

	tegra_sound: sound {
		status = "okay";
		compatible = "nvidia,tegra186-ape";
		nvidia-audio-card,name = "NVIDIA Jetson AGX Xavier APE";
		clocks = <&bpmp_clks TEGRA194_CLK_PLLA>,
			 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
			 <&bpmp_clks TEGRA194_CLK_AUD_MCLK>;
		clock-names = "pll_a", "pll_a_out0", "extern1";
		assigned-clocks = <&bpmp_clks TEGRA194_CLK_AUD_MCLK>;
		assigned-clock-parents = <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;

		nvidia-audio-card,widgets =
			"Headphone",	"CVB-RT Headphone Jack",
			"Microphone",	"CVB-RT Mic Jack",
			"Speaker",	"CVB-RT Int Spk",
			"Microphone",	"CVB-RT Int Mic",
			"Microphone",	"H40-TLV Int Mic",
			"Speaker",	"H40-TLV Int Spk"; //?

		nvidia-audio-card,routing =
			"CVB-RT Headphone Jack",     "CVB-RT HPO L Playback",
			"CVB-RT Headphone Jack",     "CVB-RT HPO R Playback",
			"CVB-RT IN1P",               "CVB-RT Mic Jack",
			"CVB-RT IN2P",               "CVB-RT Mic Jack",
			"CVB-RT Int Spk",            "CVB-RT SPO Playback",
			"CVB-RT DMIC L1",            "CVB-RT Int Mic",
			"CVB-RT DMIC L2",            "CVB-RT Int Mic",
			"CVB-RT DMIC R1",            "CVB-RT Int Mic",
			"CVB-RT DMIC R2",            "CVB-RT Int Mic",
			"H40-TLV MIC1P",             "H40-TLV Int Mic",
			"H40-TLV MIC1M",             "H40-TLV Int Mic",
			"H40-TLV MIC2P",             "H40-TLV Int Mic",
			"H40-TLV MIC2M",             "H40-TLV Int Mic",
			"H40-TLV MIC3P",             "H40-TLV Int Mic",
			"H40-TLV MIC3M",             "H40-TLV Int Mic",
			"H40-TLV MIC4P",             "H40-TLV Int Mic",
			"H40-TLV MIC4M",             "H40-TLV Int Mic",
			"H40-TLV Int Spk",            "H40-TLV CH1_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH2_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH3_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH4_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH5_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH6_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH7_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH8_OUT"; //?

		nvidia-audio-card,mclk-fs = <256>;
	};

	tegra_sound_graph: sound_graph {
		compatible = "nvidia,tegra186-audio-graph-card";

		/*
		 * Tegra audio graph card is based on uptream generic audio
		 * graph sound card. In future there is plan to use this
		 * as default sound card.
		 */
		status = "disabled";

		dais = /* ADMAIF (FE) Ports */
		       <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
		       <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
		       <&admaif10_port>, <&admaif11_port>, <&admaif12_port>,
		       <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>,
		       <&admaif19_port>, <&admaif20_port>,

		       /* ADSP (FE) Ports */
		       <&adsp_pcm1_port>, <&adsp_pcm2_port>,
		       <&adsp_compr1_port>, <&adsp_compr2_port>,

		       /* XBAR I/O ports */
		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
		       <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,

		       <&xbar_dmic1_port>, <&xbar_dmic2_port>,
		       <&xbar_dmic3_port>, <&xbar_dmic4_port>,

		       <&xbar_dspk1_port>, <&xbar_dspk2_port>,

		       /* XBAR HW accelerator ports */
		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,

		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,

		       <&xbar_afc1_in_port>, <&xbar_afc2_in_port>,
		       <&xbar_afc3_in_port>, <&xbar_afc4_in_port>,
		       <&xbar_afc5_in_port>, <&xbar_afc6_in_port>,

		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
		       <&xbar_asrc_in7_port>, <&xbar_arad_port>,

		       <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
		       <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
		       <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
		       <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
		       <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,

		       <&xbar_ope1_in_port>,

		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,

		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,

		       /* BE I/O Ports */
		       <&i2s1_port>, <&i2s2_port>, <&i2s3_port>,
		       <&i2s4_port>, <&i2s5_port>, <&i2s6_port>,

		       <&dmic1_port>, <&dmic2_port>, <&dmic3_port>,
		       <&dmic4_port>,

		       <&dspk1_port>, <&dspk2_port>,

		       /* BE HW accelerator ports */
		       <&sfc1_out_port>, <&sfc2_out_port>,
		       <&sfc3_out_port>, <&sfc4_out_port>,

		       <&mvc1_out_port>, <&mvc2_out_port>,

		       <&afc1_out_port>, <&afc2_out_port>,
		       <&afc3_out_port>, <&afc4_out_port>,
		       <&afc5_out_port>, <&afc6_out_port>,

		       <&asrc_out1_port>, <&asrc_out2_port>,
		       <&asrc_out3_port>, <&asrc_out4_port>,
		       <&asrc_out5_port>, <&asrc_out6_port>,

		       <&mixer_out1_port>, <&mixer_out2_port>,
		       <&mixer_out3_port>, <&mixer_out4_port>,
		       <&mixer_out5_port>,

		       <&ope1_out_port>,

		       <&amx1_out_port>, <&amx2_out_port>,
		       <&amx3_out_port>, <&amx4_out_port>,

		       <&adx1_out1_port>, <&adx1_out2_port>,
		       <&adx1_out3_port>, <&adx1_out4_port>,
		       <&adx2_out1_port>, <&adx2_out2_port>,
		       <&adx2_out3_port>, <&adx2_out4_port>,
		       <&adx3_out1_port>, <&adx3_out2_port>,
		       <&adx3_out3_port>, <&adx3_out4_port>,
		       <&adx4_out1_port>, <&adx4_out2_port>,
		       <&adx4_out3_port>, <&adx4_out4_port>,

		       /* ADSP related ports */
		       <&adsp_admaif1_port>, <&adsp_admaif2_port>,
		       <&adsp_admaif3_port>, <&adsp_admaif4_port>,
		       <&adsp_admaif5_port>, <&adsp_admaif6_port>,
		       <&adsp_admaif7_port>, <&adsp_admaif8_port>,
		       <&adsp_admaif9_port>, <&adsp_admaif10_port>,
		       <&adsp_admaif11_port>, <&adsp_admaif12_port>,
		       <&adsp_admaif13_port>, <&adsp_admaif14_port>,
		       <&adsp_admaif15_port>, <&adsp_admaif16_port>,
		       <&adsp_admaif17_port>, <&adsp_admaif18_port>,
		       <&adsp_admaif19_port>, <&adsp_admaif20_port>,

		       <&admaif1_codec_port>, <&admaif2_codec_port>,
		       <&admaif3_codec_port>, <&admaif4_codec_port>,
		       <&admaif5_codec_port>, <&admaif6_codec_port>,
		       <&admaif7_codec_port>, <&admaif8_codec_port>,
		       <&admaif9_codec_port>, <&admaif10_codec_port>,
		       <&admaif11_codec_port>, <&admaif12_codec_port>,
		       <&admaif13_codec_port>, <&admaif14_codec_port>,
		       <&admaif15_codec_port>, <&admaif16_codec_port>,
		       <&admaif17_codec_port>, <&admaif18_codec_port>,
		       <&admaif19_codec_port>, <&admaif20_codec_port>;

		label = "NVIDIA Jetson AGX Xavier APE";

		clocks = <&bpmp_clks TEGRA194_CLK_PLLA>,
			 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
		clock-names = "pll_a", "plla_out0";
		assigned-clocks = <&bpmp_clks TEGRA194_CLK_AUD_MCLK>;
		assigned-clock-parents = <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;

		widgets = "Headphone",	"CVB-RT Headphone Jack",
			  "Microphone", "CVB-RT Mic Jack",
			  "Speaker",	"CVB-RT Int Spk",
			  "Microphone", "CVB-RT Int Mic";

		routing = "CVB-RT Headphone Jack", "CVB-RT HPO L Playback",
			  "CVB-RT Headphone Jack", "CVB-RT HPO R Playback",
			  "CVB-RT IN1P",	   "CVB-RT Mic Jack",
			  "CVB-RT IN2P",	   "CVB-RT Mic Jack",
			  "CVB-RT Int Spk",	   "CVB-RT SPO Playback",
			  "CVB-RT DMIC L1",	   "CVB-RT Int Mic",
			  "CVB-RT DMIC L2",	   "CVB-RT Int Mic",
			  "CVB-RT DMIC R1",	   "CVB-RT Int Mic",
			  "CVB-RT DMIC R2",	   "CVB-RT Int Mic";

		/*
		 * For codec2codec based DAI link design this is required.
		 * For DPCM based design, this is optional and instead
		 * it will be picked from codec port node.
		 */
		mclk-fs = <256>;
	};
};

/*
 * Default config for all I2S dai links are
 * format = "i2s", bitclock-slave, frame-slave,
 * bitclock-noninversion, frame-noninversion,
 * Any change from default needs override on
 * platform specific files.
 */

/* Override with Codec entries */
&i2s1_to_codec {
	link-name = "rt565x-playback";
	codec {
		sound-dai = <&rt5658 0>;
		prefix = "CVB-RT";
	};
};


hdr40_snd_link_i2s: &i2s2_to_codec {
	link-name = "tlv-4-mic-array";
	/*
		format = "dsp_a";
	*/
		bitclock-master;
		frame-master;
	
	codec {
		sound-dai = <&tlvcodec 0>;
		prefix = "H40-TLV";
	};
 };

/* Override with BT SCO entries */
&i2s4_to_codec {
	format = "dsp_a";
	bitclock-inversion;
};

/* Audio graph related bindings */
&i2s1_dap_ep {
	remote-endpoint = <&rt5658_ep>;
};

&i2s4_dap_ep {
	dai-format = "dsp_a";
	bitclock-inversion;
};

hdr40_snd_i2s_dap_ep: &i2s2_dap_ep { 
	remote-endpoint = <&tlv_ep>; 
			bitclock-master;
			frame-master;

};

The driver tlv320adcx140.c in line 1005

	ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
				ADCX140_MIC_BIAS_VAL_MSK |
				ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);

dmesg

[   14.310874] tlv320adcx140-codec 1-004e: setting MIC bias failed -121
[   14.312380] tlv320adcx140-codec 1-004e: ASoC: error at snd_soc_component_probe on tlv320adcx140-codec.1-004e: -121
[   14.313491] tlv320adcx140-codec 1-004e: ASoC: failed to probe component -121
[   14.314836] tegra-asoc: sound: ASoC: failed to instantiate card -121
[   14.325877] tegra-asoc: sound: snd_soc_register_card failed (-121)
[   14.431027] tegra-asoc:: probe of sound failed with error -121

So after we removed that line in the device tree,

i2c@c240000 {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";

        tlvcodec: tlvcodec@4e {
            compatible = "ti,tlv320adc3140";
            reg = <0x4e>;
            #sound-dai-cells = <1>;

            //ti,mic-bias-source = <6>;
            ti,pdm-edge-select = <0 1 0 1>;
            ti,gpi-config = <4 5 6 7>;
            ti,gpio-config = <0 0>;
            ti,gpo-config-1 = <0 0>;
            //ti,vref-source = <2>;
            //reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
            
            	status = "okay";
            	sound-name-prefix = "H40-TLV";
            	
            	port {
			tlv_ep: endpoint {
				remote-endpoint = <&hdr40_snd_i2s_dap_ep>;
				link-name = "tlv-4-mic-array";
			};
		};
            	
        };
    };

it seems like the driver is up, and then i tried to record with the following line

arecord -D hw:1,1 -f cd -t wav -d 5 -c 4 test.wav
Recording WAVE 'test.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Channels 4
arecord: pcm_read:2178: read error: Input/output error

and this is the error we get in the dmesg

[  267.552704] tegra210-i2s 2901100.i2s: timeout: failed to reset I2S for capture
[  267.552913] tegra210-i2s 2901100.i2s: ASoC: PRE_PMU: I2S2 TX event failed: -110
[  277.723604] tlv320adcx140-codec 1-004e: ASoC: error at snd_soc_component_update_bits on tlv320adcx140-codec.1-004e: -121

I tried to config the i2s entry with amixer like it describe in NVIDIA, but I'm not sure i did it right, and maybe this codec need some more configs before I can recored with it

AudioSetupAndDevelopment

amixer -c APE cset name='ADMAIF2 Mux' 'I2S2'
numid=1308,iface=MIXER,name='ADMAIF2 Mux'
  ; type=ENUMERATED,access=rw------,values=1,items=81
  ; Item #0 'None'
  ; Item #1 'ADMAIF1'
  ; Item #2 'ADMAIF2'
  ; Item #3 'ADMAIF3'
  ; Item #4 'ADMAIF4'
  ; Item #5 'ADMAIF5'
  ; Item #6 'ADMAIF6'
  ; Item #7 'ADMAIF7'
  ; Item #8 'ADMAIF8'
  ; Item #9 'ADMAIF9'
  ; Item #10 'ADMAIF10'
  ; Item #11 'ADMAIF11'
  ; Item #12 'ADMAIF12'
  ; Item #13 'ADMAIF13'
  ; Item #14 'ADMAIF14'
  ; Item #15 'ADMAIF15'
  ; Item #16 'ADMAIF16'
  ; Item #17 'I2S1'
  ; Item #18 'I2S2'
  ; Item #19 'I2S3'
  ; Item #20 'I2S4'
  ; Item #21 'I2S5'
  ; Item #22 'I2S6'
  ; Item #23 'SFC1'
  ; Item #24 'SFC2'
  ; Item #25 'SFC3'
  ; Item #26 'SFC4'
  ; Item #27 'MIXER1 TX1'
  ; Item #28 'MIXER1 TX2'
  ; Item #29 'MIXER1 TX3'
  ; Item #30 'MIXER1 TX4'
  ; Item #31 'MIXER1 TX5'
  ; Item #32 'AMX1'
  ; Item #33 'AMX2'
  ; Item #34 'AMX3'
  ; Item #35 'AMX4'
  ; Item #36 'ARAD1'
  ; Item #37 'AFC1'
  ; Item #38 'AFC2'
  ; Item #39 'AFC3'
  ; Item #40 'AFC4'
  ; Item #41 'AFC5'
  ; Item #42 'AFC6'
  ; Item #43 'OPE1'
  ; Item #44 'SPKPROT1'
  ; Item #45 'MVC1'
  ; Item #46 'MVC2'
  ; Item #47 'IQC1-1'
  ; Item #48 'IQC1-2'
  ; Item #49 'IQC2-1'
  ; Item #50 'IQC2-2'
  ; Item #51 'DMIC1'
  ; Item #52 'DMIC2'
  ; Item #53 'DMIC3'
  ; Item #54 'DMIC4'
  ; Item #55 'ADX1 TX1'
  ; Item #56 'ADX1 TX2'
  ; Item #57 'ADX1 TX3'
  ; Item #58 'ADX1 TX4'
  ; Item #59 'ADX2 TX1'
  ; Item #60 'ADX2 TX2'
  ; Item #61 'ADX2 TX3'
  ; Item #62 'ADX2 TX4'
  ; Item #63 'ADX3 TX1'
  ; Item #64 'ADX3 TX2'
  ; Item #65 'ADX3 TX3'
  ; Item #66 'ADX3 TX4'
  ; Item #67 'ADX4 TX1'
  ; Item #68 'ADX4 TX2'
  ; Item #69 'ADX4 TX3'
  ; Item #70 'ADX4 TX4'
  ; Item #71 'ADMAIF17'
  ; Item #72 'ADMAIF18'
  ; Item #73 'ADMAIF19'
  ; Item #74 'ADMAIF20'
  ; Item #75 'ASRC1 TX1'
  ; Item #76 'ASRC1 TX2'
  ; Item #77 'ASRC1 TX3'
  ; Item #78 'ASRC1 TX4'
  ; Item #79 'ASRC1 TX5'
  ; Item #80 'ASRC1 TX6'
  : values=18

Usually an input/output error is because the device is not targetted properly or because the clocks are incorrect. Check your arecord -l as well as the clocks you expect vs the clocks that are sending to the codec.

I must send clocks to the device via the device tree? and to physically connect some clock from the Jetson to the device?

I don't think that i'm sending right now any clock

arecord -l
**** List of CAPTURE Hardware Devices ****
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 0: tegra-dlink-0 XBAR-ADMAIF1-0 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 1: tegra-dlink-1 XBAR-ADMAIF2-1 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 2: tegra-dlink-2 XBAR-ADMAIF3-2 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 3: tegra-dlink-3 XBAR-ADMAIF4-3 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 4: tegra-dlink-4 XBAR-ADMAIF5-4 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 5: tegra-dlink-5 XBAR-ADMAIF6-5 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 6: tegra-dlink-6 XBAR-ADMAIF7-6 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 7: tegra-dlink-7 XBAR-ADMAIF8-7 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 8: tegra-dlink-8 XBAR-ADMAIF9-8 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 9: tegra-dlink-9 XBAR-ADMAIF10-9 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 10: tegra-dlink-10 XBAR-ADMAIF11-10 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 11: tegra-dlink-11 XBAR-ADMAIF12-11 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 12: tegra-dlink-12 XBAR-ADMAIF13-12 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 13: tegra-dlink-13 XBAR-ADMAIF14-13 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 14: tegra-dlink-14 XBAR-ADMAIF15-14 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 15: tegra-dlink-15 XBAR-ADMAIF16-15 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 16: tegra-dlink-16 XBAR-ADMAIF17-16 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 17: tegra-dlink-17 XBAR-ADMAIF18-17 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 18: tegra-dlink-18 XBAR-ADMAIF19-18 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 19: tegra-dlink-19 XBAR-ADMAIF20-19 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 20: tegra-dlink-20 ADSP-FE1-20 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: APE [NVIDIA Jetson AGX Xavier APE], device 21: tegra-dlink-21 ADSP-FE2-21 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0

It doesn't look like the TI codec is registering at all with your list of audio devices from arecord. Check that it is plugged in and the AC-MB is set to USB audio source. If you are using the EVM, there is no need for external clocks because the USB provides clocks. You can read the EVM user guide here for more description of the jumpers required to set the audio signal path desired: https://www.ti.com/lit/ug/sbau359a/sbau359a.pdf

We are not using AC-MB, we are connecting PCMD3140 directly to our jetson 40 pin i2s entry

Ok, sorry about that. 

Are you sure the codec is connected to I2S2 of the Jetson? Reading this forum post they had the same issue as you and was solved by changing the amixer -c APE command.

If you are connected to the I2S pins that you expect, can you make sure that they are providing clocks with an oscilloscope? You will need at least BCLK and WCLK to be going into the codec if the codec is operating in target mode, and you would need MCLK to go into the codec if it is operating in controller mode (it would generate its own BCLK and WCLK from this). To set in controller mode (also called master mode), you will include the lines "bitclock-master; frame-master;" in your dts file under the audio card's section. I see you included these lines in the "hdr40_snd_link_i2s: &i2s2_to_codec" and "hdr40_snd_i2s_dap_ep: &i2s2_dap_ep" sections, I'm not sure what these are. If the codec should be in master mode, you will need to make sure that it knows, so it can generate its own BCLK and WCLK, since by default the codec will be in target (or "slave") mode. Let me know what the clock outputs are on the I2S connected pins so we can figure out what to do next.

The setup for our PCMD3140 taking from here ADCx120EVM-PDK, PCMD3140EVM-PDK Evaluation Module page 11(we are using only PCMD3140 without AC-MB)

pcmd3140.pdf

We connected the I2C channels directly to the Xavier 40-pin header. Additionally, we connected the I2S pins (SDOUT, BCLK, FSYNC) from the PCMD3140 directly to the 40-pin header on the Xavier, where they correspond to I2S2 as per the pin-gpio-expansion-header specification. pin-gpio-expansion-header.

The goal is to configure the Xavier as the master device and have it push the clock to the BCLK pin.

We tried the following device tree configuration to enable the setup:

// SPDX-License-Identifier: GPL-2.0-only
/*
 * T194 p2822-0000 audio common DTSI file.
 *
 * Copyright (c) 2017-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 *
 */

#include <audio/tegra-platforms-audio-dai-links.dtsi>
#include <audio/tegra186-audio-dai-links.dtsi>
#include <audio/tegra186-audio-graph.dtsi>
#include <dt-bindings/gpio/tegra194-gpio.h>
#include <dt-bindings/audio/tegra194-audio.h>
#include <audio/tegra-platforms-audio-dmic3-5-switch.dtsi>
#include <dt-bindings/gpio/gpio.h>
/ {

	aconnect@2a41000 {
		status = "okay";

		agic-controller@2a41000 {
			status = "okay";
		};

		adsp@2993000 {
			status = "okay";
		};
	};

	i2c@c250000 {
		rt5658: rt5659.7-001a@1a {
			compatible = "realtek,rt5658";
			reg = <0x1a>;

			/* refer include/sound/rt5659.h for the values to be used */
			realtek,jd-src = <2>; /* RT5659_JD_HDA_HEADER */
			realtek,dmic1-data-pin = <0>; /* RT5659_DMIC1_NULL */
			realtek,dmic2-data-pin = <0>; /* RT5659_DMIC2_NULL */

			/* Codec IRQ output */
			interrupt-parent = <&tegra_main_gpio>;
			interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>;

			clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
			clock-names = "mclk";

			#sound-dai-cells = <1>;

			sound-name-prefix = "CVB-RT";

			status = "okay";

			port {
				rt5658_ep: endpoint {
					remote-endpoint = <&i2s1_dap_ep>;
					mclk-fs = <256>;
					link-name = "rt565x-playback";
				};
			};
		};
	};

	// our Sound settings
	
//	&hdr40_i2c0 {
	i2c@c240000 {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";

        tlvcodec: tlvcodec@4e {
            compatible = "ti,tlv320adc3140";
            reg = <0x4e>;
            #sound-dai-cells = <1>;

            ti,mic-bias-source = <0>;
            ti,vref-source = <0>;
            //ti,pdm-edge-select = <0 1 0 0>;
            
            ti,gpi-config = <4 5 0 0>;
            ti,gpio-config = <0 0>;
            ti,gpo-config-1 = <4 1>;
            
            //reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
            
            	status = "okay";
            	sound-name-prefix = "H40-TLV";
            	
            	port {
			tlv_ep: endpoint {
				remote-endpoint = <&hdr40_snd_i2s_dap_ep>;
				link-name = "tlv-4-mic-array";
			};
		};
            	
        };
    };

	/* Default for all I2S is long fsync width(31) */
	aconnect@2a41000 {
		ahub {
			/* I2S4 in Short frame sync for BT SCO */
			i2s@2901300 {
				bclk-ratio = <4>;
			};
		};
	};

	tegra_acsl_audio: acsl_audio {
		status = "okay";
	};

	hda@3510000 {
		status = "okay";

		nvidia,model = "NVIDIA Jetson AGX Xavier HDA";
	};

	tegra_sound: sound {
		status = "okay";
		compatible = "nvidia,tegra186-ape";
		nvidia-audio-card,name = "NVIDIA Jetson AGX Xavier APE";
		clocks = <&bpmp_clks TEGRA194_CLK_PLLA>,
			 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
			 <&bpmp_clks TEGRA194_CLK_AUD_MCLK>;
		clock-names = "pll_a", "pll_a_out0", "extern1";
		assigned-clocks = <&bpmp_clks TEGRA194_CLK_AUD_MCLK>;
		assigned-clock-parents = <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;

		nvidia-audio-card,widgets =
			"Headphone",	"CVB-RT Headphone Jack",
			"Microphone",	"CVB-RT Mic Jack",
			"Speaker",	"CVB-RT Int Spk",
			"Microphone",	"CVB-RT Int Mic",
			"Microphone",	"H40-TLV Int Mic1",
			"Microphone",	"H40-TLV Int Mic2",
			"Microphone",	"H40-TLV Int Mic3",
			"Microphone",	"H40-TLV Int Mic4";
			/*"Speaker",	"H40-TLV Int Spk"; //?*/

		nvidia-audio-card,routing =
			"CVB-RT Headphone Jack",     "CVB-RT HPO L Playback",
			"CVB-RT Headphone Jack",     "CVB-RT HPO R Playback",
			"CVB-RT IN1P",               "CVB-RT Mic Jack",
			"CVB-RT IN2P",               "CVB-RT Mic Jack",
			"CVB-RT Int Spk",            "CVB-RT SPO Playback",
			"CVB-RT DMIC L1",            "CVB-RT Int Mic",
			"CVB-RT DMIC L2",            "CVB-RT Int Mic",
			"CVB-RT DMIC R1",            "CVB-RT Int Mic",
			"CVB-RT DMIC R2",            "CVB-RT Int Mic",
			"H40-TLV MIC1P",             "H40-TLV Int Mic1",
			"H40-TLV MIC1M",             "H40-TLV Int Mic1",
			"H40-TLV MIC2P",             "H40-TLV Int Mic2",
			"H40-TLV MIC2M",             "H40-TLV Int Mic2",
			"H40-TLV MIC3P",             "H40-TLV Int Mic3",
			"H40-TLV MIC3M",             "H40-TLV Int Mic3",
			"H40-TLV MIC4P",             "H40-TLV Int Mic4",
			"H40-TLV MIC4M",             "H40-TLV Int Mic4";//,
			/*"H40-TLV Int Spk",            "H40-TLV CH1_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH2_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH3_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH4_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH5_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH6_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH7_OUT", //?
			"H40-TLV Int Spk",            "H40-TLV CH8_OUT"; //?*/

		nvidia-audio-card,mclk-fs = <256>;
	};

	tegra_sound_graph: sound_graph {
		compatible = "nvidia,tegra186-audio-graph-card";

		/*
		 * Tegra audio graph card is based on uptream generic audio
		 * graph sound card. In future there is plan to use this
		 * as default sound card.
		 */
		status = "disabled";

		dais = /* ADMAIF (FE) Ports */
		       <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
		       <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
		       <&admaif10_port>, <&admaif11_port>, <&admaif12_port>,
		       <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>,
		       <&admaif19_port>, <&admaif20_port>,

		       /* ADSP (FE) Ports */
		       <&adsp_pcm1_port>, <&adsp_pcm2_port>,
		       <&adsp_compr1_port>, <&adsp_compr2_port>,

		       /* XBAR I/O ports */
		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
		       <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,

		       <&xbar_dmic1_port>, <&xbar_dmic2_port>,
		       <&xbar_dmic3_port>, <&xbar_dmic4_port>,

		       <&xbar_dspk1_port>, <&xbar_dspk2_port>,

		       /* XBAR HW accelerator ports */
		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,

		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,

		       <&xbar_afc1_in_port>, <&xbar_afc2_in_port>,
		       <&xbar_afc3_in_port>, <&xbar_afc4_in_port>,
		       <&xbar_afc5_in_port>, <&xbar_afc6_in_port>,

		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
		       <&xbar_asrc_in7_port>, <&xbar_arad_port>,

		       <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
		       <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
		       <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
		       <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
		       <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,

		       <&xbar_ope1_in_port>,

		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,

		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,

		       /* BE I/O Ports */
		       <&i2s1_port>, <&i2s2_port>, <&i2s3_port>,
		       <&i2s4_port>, <&i2s5_port>, <&i2s6_port>,

		       <&dmic1_port>, <&dmic2_port>, <&dmic3_port>,
		       <&dmic4_port>,

		       <&dspk1_port>, <&dspk2_port>,

		       /* BE HW accelerator ports */
		       <&sfc1_out_port>, <&sfc2_out_port>,
		       <&sfc3_out_port>, <&sfc4_out_port>,

		       <&mvc1_out_port>, <&mvc2_out_port>,

		       <&afc1_out_port>, <&afc2_out_port>,
		       <&afc3_out_port>, <&afc4_out_port>,
		       <&afc5_out_port>, <&afc6_out_port>,

		       <&asrc_out1_port>, <&asrc_out2_port>,
		       <&asrc_out3_port>, <&asrc_out4_port>,
		       <&asrc_out5_port>, <&asrc_out6_port>,

		       <&mixer_out1_port>, <&mixer_out2_port>,
		       <&mixer_out3_port>, <&mixer_out4_port>,
		       <&mixer_out5_port>,

		       <&ope1_out_port>,

		       <&amx1_out_port>, <&amx2_out_port>,
		       <&amx3_out_port>, <&amx4_out_port>,

		       <&adx1_out1_port>, <&adx1_out2_port>,
		       <&adx1_out3_port>, <&adx1_out4_port>,
		       <&adx2_out1_port>, <&adx2_out2_port>,
		       <&adx2_out3_port>, <&adx2_out4_port>,
		       <&adx3_out1_port>, <&adx3_out2_port>,
		       <&adx3_out3_port>, <&adx3_out4_port>,
		       <&adx4_out1_port>, <&adx4_out2_port>,
		       <&adx4_out3_port>, <&adx4_out4_port>,

		       /* ADSP related ports */
		       <&adsp_admaif1_port>, <&adsp_admaif2_port>,
		       <&adsp_admaif3_port>, <&adsp_admaif4_port>,
		       <&adsp_admaif5_port>, <&adsp_admaif6_port>,
		       <&adsp_admaif7_port>, <&adsp_admaif8_port>,
		       <&adsp_admaif9_port>, <&adsp_admaif10_port>,
		       <&adsp_admaif11_port>, <&adsp_admaif12_port>,
		       <&adsp_admaif13_port>, <&adsp_admaif14_port>,
		       <&adsp_admaif15_port>, <&adsp_admaif16_port>,
		       <&adsp_admaif17_port>, <&adsp_admaif18_port>,
		       <&adsp_admaif19_port>, <&adsp_admaif20_port>,

		       <&admaif1_codec_port>, <&admaif2_codec_port>,
		       <&admaif3_codec_port>, <&admaif4_codec_port>,
		       <&admaif5_codec_port>, <&admaif6_codec_port>,
		       <&admaif7_codec_port>, <&admaif8_codec_port>,
		       <&admaif9_codec_port>, <&admaif10_codec_port>,
		       <&admaif11_codec_port>, <&admaif12_codec_port>,
		       <&admaif13_codec_port>, <&admaif14_codec_port>,
		       <&admaif15_codec_port>, <&admaif16_codec_port>,
		       <&admaif17_codec_port>, <&admaif18_codec_port>,
		       <&admaif19_codec_port>, <&admaif20_codec_port>;

		label = "NVIDIA Jetson AGX Xavier APE";

		clocks = <&bpmp_clks TEGRA194_CLK_PLLA>,
			 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
		clock-names = "pll_a", "plla_out0";
		assigned-clocks = <&bpmp_clks TEGRA194_CLK_AUD_MCLK>;
		assigned-clock-parents = <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;

		widgets = "Headphone",	"CVB-RT Headphone Jack",
			  "Microphone", "CVB-RT Mic Jack",
			  "Speaker",	"CVB-RT Int Spk",
			  "Microphone", "CVB-RT Int Mic";

		routing = "CVB-RT Headphone Jack", "CVB-RT HPO L Playback",
			  "CVB-RT Headphone Jack", "CVB-RT HPO R Playback",
			  "CVB-RT IN1P",	   "CVB-RT Mic Jack",
			  "CVB-RT IN2P",	   "CVB-RT Mic Jack",
			  "CVB-RT Int Spk",	   "CVB-RT SPO Playback",
			  "CVB-RT DMIC L1",	   "CVB-RT Int Mic",
			  "CVB-RT DMIC L2",	   "CVB-RT Int Mic",
			  "CVB-RT DMIC R1",	   "CVB-RT Int Mic",
			  "CVB-RT DMIC R2",	   "CVB-RT Int Mic";

		/*
		 * For codec2codec based DAI link design this is required.
		 * For DPCM based design, this is optional and instead
		 * it will be picked from codec port node.
		 */
		mclk-fs = <256>;
	};
};

/*
 * Default config for all I2S dai links are
 * format = "i2s", bitclock-slave, frame-slave,
 * bitclock-noninversion, frame-noninversion,
 * Any change from default needs override on
 * platform specific files.
 */

/* Override with Codec entries */
&i2s1_to_codec {
	link-name = "rt565x-playback";
	codec {
		sound-dai = <&rt5658 0>;
		prefix = "CVB-RT";
	};
};


hdr40_snd_link_i2s: &i2s2_to_codec {
	link-name = "tlv-4-mic-array";
	/*
		format = "dsp_a";
	*/
		//bitclock-master;
		//frame-master;
	
	codec {
		sound-dai = <&tlvcodec 0>;
		prefix = "H40-TLV";
		clock-frequency = <44100>;
	};
 };

/* Override with BT SCO entries */
&i2s4_to_codec {
	format = "dsp_a";
	bitclock-inversion;
};

/* Audio graph related bindings */
&i2s1_dap_ep {
	remote-endpoint = <&rt5658_ep>;
};

&i2s4_dap_ep {
	dai-format = "dsp_a";
	bitclock-inversion;
};

hdr40_snd_i2s_dap_ep: &i2s2_dap_ep { 
	remote-endpoint = <&tlv_ep>; 
			//bitclock-master;
			//frame-master;

};

We also entered the following command into amixer as described in the examples-i2s documentation: examples-i2s

amixer -c APE cset name='ADMAIF2 Mux' 'I2S2'
numid=1308,iface=MIXER,name='ADMAIF2 Mux'
  ; type=ENUMERATED,access=rw------,values=1,items=81
  ; Item #0 'None'
  ; Item #1 'ADMAIF1'
  ; Item #2 'ADMAIF2'
  ; Item #3 'ADMAIF3'
  ; Item #4 'ADMAIF4'
  ; Item #5 'ADMAIF5'
  ; Item #6 'ADMAIF6'
  ; Item #7 'ADMAIF7'
  ; Item #8 'ADMAIF8'
  ; Item #9 'ADMAIF9'
  ; Item #10 'ADMAIF10'
  ; Item #11 'ADMAIF11'
  ; Item #12 'ADMAIF12'
  ; Item #13 'ADMAIF13'
  ; Item #14 'ADMAIF14'
  ; Item #15 'ADMAIF15'
  ; Item #16 'ADMAIF16'
  ; Item #17 'I2S1'
  ; Item #18 'I2S2'
  ; Item #19 'I2S3'
  ; Item #20 'I2S4'
  ; Item #21 'I2S5'
  ; Item #22 'I2S6'
  ; Item #23 'SFC1'
  ; Item #24 'SFC2'
  ; Item #25 'SFC3'
  ; Item #26 'SFC4'
  ; Item #27 'MIXER1 TX1'
  ; Item #28 'MIXER1 TX2'
  ; Item #29 'MIXER1 TX3'
  ; Item #30 'MIXER1 TX4'
  ; Item #31 'MIXER1 TX5'
  ; Item #32 'AMX1'
  ; Item #33 'AMX2'
  ; Item #34 'AMX3'
  ; Item #35 'AMX4'
  ; Item #36 'ARAD1'
  ; Item #37 'AFC1'
  ; Item #38 'AFC2'
  ; Item #39 'AFC3'
  ; Item #40 'AFC4'
  ; Item #41 'AFC5'
  ; Item #42 'AFC6'
  ; Item #43 'OPE1'
  ; Item #44 'SPKPROT1'
  ; Item #45 'MVC1'
  ; Item #46 'MVC2'
  ; Item #47 'IQC1-1'
  ; Item #48 'IQC1-2'
  ; Item #49 'IQC2-1'
  ; Item #50 'IQC2-2'
  ; Item #51 'DMIC1'
  ; Item #52 'DMIC2'
  ; Item #53 'DMIC3'
  ; Item #54 'DMIC4'
  ; Item #55 'ADX1 TX1'
  ; Item #56 'ADX1 TX2'
  ; Item #57 'ADX1 TX3'
  ; Item #58 'ADX1 TX4'
  ; Item #59 'ADX2 TX1'
  ; Item #60 'ADX2 TX2'
  ; Item #61 'ADX2 TX3'
  ; Item #62 'ADX2 TX4'
  ; Item #63 'ADX3 TX1'
  ; Item #64 'ADX3 TX2'
  ; Item #65 'ADX3 TX3'
  ; Item #66 'ADX3 TX4'
  ; Item #67 'ADX4 TX1'
  ; Item #68 'ADX4 TX2'
  ; Item #69 'ADX4 TX3'
  ; Item #70 'ADX4 TX4'
  ; Item #71 'ADMAIF17'
  ; Item #72 'ADMAIF18'
  ; Item #73 'ADMAIF19'
  ; Item #74 'ADMAIF20'
  ; Item #75 'ASRC1 TX1'
  ; Item #76 'ASRC1 TX2'
  ; Item #77 'ASRC1 TX3'
  ; Item #78 'ASRC1 TX4'
  ; Item #79 'ASRC1 TX5'
  ; Item #80 'ASRC1 TX6'
  : values=18

Next, we attempted to record audio using the following command:

arecord -D hw:APE,1 -f cd -t wav -d 5 -c 4 test.wav
Recording WAVE 'test.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Channels 4

Despite the correct configuration and command, the oscilloscope showed no clock signal on either the BCLK or PDMCLK pins. However, the I2C pin showed activity, indicating that communication was happening.

Additionally, when attempting to record using a single channel:

arecord -D hw:APE,1 -f cd -t wav -d 5 -c 1 test.wav
Recording WAVE 'test.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Mono
arecord: pcm_read:2178: read error: Input/output error

We are not entirely sure what values to specify for the widgets and routing paths in the device tree.

We also need guidance on how to properly configure the Jetson Xavier to act as the master and drive the BCLK signal.

We would greatly appreciate any insights or suggestions you may have to help us resolve these issues and successfully configure the PCMD3140 with the Xavier.

Thank you very much!

Hi,

You will need clock signals into the device to record, that is why you see the input/output error. To get this working, this is more of a Jetson support problem and not something TI can support. I found this forum post: https://forums.developer.nvidia.com/t/jetson-xavier-nx-i2s-with-pcm1808/246423 that describes how you have to set the Jetson as the BCLK and FCLK master with amixer command, and then you have to configure the expansion header to enable the I2S pins and enable the clocks: https://docs.nvidia.com/jetson/archives/r34.1/DeveloperGuide/text/HR/ConfiguringTheJetsonExpansionHeaders.html?highlight=jetson%20io

Once you get the clocks outputting from the Jetson and if you are still having issues with recording, I may be able to help more. If you still have issues with the clocks, I would recommend posting on the Nvidia forums.

We are now manging to get data from the i2s clock that enters in the BCLK, and also we see with a scope that the PDM clocks are working and also that data is going out from the PDM microphones, but we are not getting any data in  SDOUT.

Hi,

You're going to need to set the audio card routing with the device-specific routing parameters, these can be found in the "snd_soc_dapm_route" struct in the adcx140 driver. You should also make sure that you have clock going into the FCLK as well.