Tool/software:
Hi team,
On behalf of my customer, I would like to post a question to seek your guidance:

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Tool/software:
Hi team,
On behalf of my customer, I would like to post a question to seek your guidance:
Hi Khoi,
From a hardware perspective the customer can try to implement a RC filter at the input stage or a bandpass filter that is targeted to customer input signal.
On the ASI clocks, you can try to reduce BCLK to (2ch * 16bit * 48khz) = 1.536MHz
I would also check schematic for proper decoupling of the power supply as this can be a common source for noise and transients in the system.
Hi Daveon,
Thanks for the recommendation. I have sent the schematic via email to you.
Hi Khoie,
Thanks for sharing offline. There are no concerns that I see.
Can you share an oscilloscope view of your ASI clocks?
Hi Tuan,
Daveon is out of office and will return to answer your question on Monday. Please wait for a response for him.
Thank you,
Jeff McPherson
Hi Tuan,
Since the device is in i2s mode the BCLK should be greater than or equal to 2 Ch * 16bit word length * 48kHz FS = 1.536MHz.
Fsync should remain 48kHz. SCKI can remain 256*Fs at 12.228MHz. In the oscilloscope view you want to check that the clocks are the correct frequencies and synchronized so that audio is processed clear without any distortion.
It is important that these are synchronized in this device due to its fade-in architecture. Otherwise, you will see distortion, this is explained in section 7.3.3 of the d/s.
Try recording a 1kHz sine wave and note the response for a better analyzation of the issue.