SRC4392: Large Jitter on DIT output

Hello Mochi, 

There is no max jitter in datasheet, even if the  jitter is too high,   technically there is no limit mentioned. Nevertheless,  the SRC in the SRC4392 has been enhanced to provide exceptional jitter attenuation characteristics, helping to improve overall application performance.

What clks are you providing to the device? for example the datasheet mentions that it is recommended that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for optimal performance. In general, phase-locked loop (PLL) clock synthesizers should be avoided, unless they are designed and/or specified for low clock jitter.

If you are measuring 1900ps at 48k, then in terms of UI  ( jitter per interval)  it would  not be 16.8e-3 UI, am i missing something here? 

Regards,

Arash

Hi Arash,

 This is EOL replacement activity, our customer modified PCB from competitors SRC device to SRC4392.

There is same X'tal clock MCK input and measured at 128fs of 48KHz AEC/EBU output data.

The original device has 1.4mUI jitter performance, it is less than 1/10 from SRC4392.

Is there any suggestion to improve this jitter?   

 Regards,

Mochizuki

Hello

To minimize jitter you can improve the slew rate of the clock edges, filter the clks, and also watch the noise on supplies among other factors.

Are they using 2 different boards to compare the measurements  or it is a pin to pin compatible  and thus the same board is being used?  The 2 jitter waveforms look different in behaviour as well as magnitude.

Can you compare the other IC's datasheet  and see if jitter spec matches with 1.4mUI they actually measured?

If the boards are fairly similar,  then i would try with several different samples of SRC4392 to see if they show such high jitter. 

https://resources.pcb.cadence.com/blog/2022-how-to-eliminate-clock-jitter

Regards,

Arash

Arash,

Our customer newly created PCB for SRC4392, which is not P2P device.

Could you accept to have e-mail communication because of confidential design data I want to send you.

Regards,

Mochizuki