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TAS6424E-Q1: VDD POR bit behavior depends on Standby pin

Kazuki Kuramochi
Genius 9455 points
Part Number: TAS6424E-Q1
Other Parts Discussed in Thread: TAS6424-Q1, TAS6424

Tool/software:

Hello Expert,

Could we clear VDD POR bit(0x13 bit4) during standby is low but VDD is stable around 3.3V?

I understood we can communicate with this device through I2C if standby is low but customer may observed that VDD POR haven't cleared by MISC Ctrl3 at this condition...
So I'd like to make sure about this point just in case for confirming root cause.

Best regards,
Kazuki Kuramochi

  • 0
    TI__Mastermind 40060 points

    Hi Kuramochi-san

      Perhaps there's some misunderstanding. I use EVM to have a try, by just pulling down STANDBY pin, the VDD POR won't be set. Only with power off and re-power up, this bit would be set. Is there any other details we are missing?

  • 0 in reply to Shadow He
    TI__Genius 9455 points

    Hi Shadow-san,

    Thank you for your confirmation.

    My questions is not for the behavior of VDD POR bit "when" we pull /STANDBY to low.
    Our understanding for VDD POR is require to clear by MISC3 for clearing VDD POR bit result.
    Also, we understood that we can clear VDDPOR bit by MISC3 "during" /STANDBY is high.

    We want to know about whether we can clear VDD POR bit by MISC3 "during" /STANDBY is low from the viewpoint of IC design.
    Could you please tell me about this point?

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Mastermind 40060 points

    Hi Kuramochi-san

    Kazuki Kuramochi said:
    We want to know about whether we can clear VDD POR bit by MISC3 "during" /STANDBY is low from the viewpoint of IC design.

    Yes, could clear during STANDBY pin low.

    For this device, pull low STANDBY won't clear the register settings, so needn't keep set this VDD POR bit.

  • 0 in reply to Shadow He
    TI__Genius 9455 points

    Hi Shadow-san,

    Thank you for your confirmation.
    I understand that TAS6424E-Q1 is design as VDD POR can be clear during STANDBY=LOW by MISC3.

    On the other hands, customer confirmed following behavior.
    STANDBY=LOW : VDD POR haven't cleared by MISC3
    STANDBY=HIGH : VDD POR cleared by MISC3

    Is there any expected root cause?

    Currently, their system is doing initialization including clear fault during STANBY=LOW.
    This is because MISC5 PHASE_SEL require configuring this during STANBY=LOW.
    Then, they observed above behavior so they are asking about expected behavior from the view point of IC design and  expected root cause.

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Genius 10160 points

    Kuramochi-san,

    Did a bench test, the result is as customer measured: at standby L status, this bit can't be cleared.  As the device is designed at too long time before, we can't figure out how the logic is. So please treat this behavior as it is.

    Dylan

  • 0 in reply to Dylan Yao
    TI__Genius 9455 points

    Hi Dylan-san,

    Thank you for your confirmation.
    Unfortunately, I don't have TAS6424"E"-Q1 EVM therefore I tested TAS6424-Q1 EVM.
    The test summary regarding FAULT/WARN and STANDBY pin is as below.

    1. Standby pin = HIGH
      1. FAULT(OV/OC) = It could be cleared by MISC3
      2. WARN(POR/OTW) = it could be cleared by MISC3
    2. Standby pin = LOW
      1. FAULT(OV/OV) = those registers cleared when Standby pin is toggled to low, it don't need to use MISC3.
      2. WARN(POR/OTW) = it couldn't cleared by MISC3

    Based on this test result, I guess WARN register cannot be cleared by STANDBY pin = Low condition.
    How do you think about it?

    I understand this question is difficult question but TAS6424x-Q1 family is our Hero device for automotive applications and those device's status is "Active".
    So I think we need to prepare the answer which we can guaranty and it should not be lead by try and error.
    At least, I think we need to explain about expected correlation between WARN/STANDBY/MISC from the view point of design.

    Best regards,
    Kazuki Kuramochi

  • +1 in reply to Kazuki Kuramochi
    TI__Genius 10160 points

    Kuramochi-san,

    The better way to clarify this is:

    1. at Standby pin L status: all other blocks(digital status machine, analog signal chain, oscillator and clock system) are shutdown, except digital registers with write capability.   All read-only registers are not trustable, as other domain circuit are not functional, so any of reported fault is not correct, also can't be cleared because no reaction from analog circuit.

    2. at standby pin H status: all circuit is running, and device can behavior correctly.

    At standby pin L status, IIC open to customer is to enable a IIC configuration operation, not to be used as a normal way to operate device. So any of the action more than register configuration should not be conducted.

    Dylan

  • 0 in reply to Dylan Yao
    TI__Genius 9455 points

    Hi Dylan,

    I understand our stand point.
    I explained as below.

    I2C access during STNADBY=LOW is only intended to use initialization for R/W registers.
    So we don't expected to use I2C access during STADBY=LOW for monitoring Read only register and changing Read only register by R/W register during this condition.
    Therefore, their observed behavior is expected.

    If I received additional question or concern, I'll let you know.

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Genius 10160 points

    Thanks. get back to us if more questions. close this thread now.