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PCM9211: SPDIF lock issue in 192kHz

Felipe Delgado
Prodigy 10 points
Part Number: PCM9211


Tool/software:

Hello,

I am encountering an issue with the PCM9211 chip regarding the detection of 192kHz audio streams via the DIR lock feature. While the chip performs as expected for other sampling rates (44.1kHz, 48kHz, 96kHz, and 176.4kHz) and provides data at the I2S output, it fails to decode SPDIF at 192kHz.

To provide a clearer understanding of our system, please find the hardware details below:

  • An external 24.576 MCLK is supplied at XTI pin of the chip.
  • The SPDIF source comes from coaxial connector. The signal passes through an isolation transformer (1:1), then a 75Ω termination resistor and a 100nF capacitor in series before entering at RXIN0 input of the chip. The signal ground from coaxial connector is only connected to board ground next to the input of the IC. (See the image below)
  • For DIR and PLL loop filter, we used the recommended components from the datasheet.

On the software side, we left all the registers at their default states except the input selection register, which was configured to switch inputs as needed.

The PCM9211 fails to decode SPDIF with a 192kHz sampling frequency and we noticed that the frequency of the incoming signal, as detected by the chip, is unstable showing multiple sampling frequency changes. We attempted to change the registers 30h to modify the PLL clock ratio and 31h the XTI clock settings but without success.

We would greatly appreciate any advice or insights on addressing this issue. Has anyone else experienced similar behavior with the PCM9211 at 192kHz?

Thank you for your support!

Best regards.

Felipe Delgado

  • 0
    TI__Mastermind 31041 points

    Hello Felipe,

    I don't recall I have  seen this issue in the past and  considering this is a very mature part, if it was the problem of the chip it would have been reported by now so most probably it is either a component at the input path to the chip or its a simple set up issue.

    Is it possible to connect the S/PDIF without the transformer or even the AC coupling and  termination resistor? I am not sure if any of these components could be distorting the input signal at higher sampling frequency, but it worth  checking as sometimes the  components at the input , distorted the input signal such that the device could not lock on to the fs.

    XMCKO (the XTI clock buffered output) provides a buffered (and divided) XTI clock that can be output to MPIO_A. In XTI mode, the output clocks (SCKO, BCKO, and LRCKO) are generated from the XTI source clock. When monitoring these signals, do you see anything out of ordinary?

    The PCM9211 has two integrated sampling frequency calculators. The first calculator is always connected to the output of the DIR. It calculates the actual sampling frequency of the incoming S/PDIF signal. The result can be read from a register, or output through the MPIO pins. Please refer to  section 7.3.8.6.9  and 7.3.8.6.10

    In  register 31, when you set the BCK and LRCLK setting, you set BCK according to BCK= # of Ch  x  Channel depth  x  Fs ( just do a sanity check) 

    Have you confirmed that the clock you are providing meets the spec for XTI  input clock duty cycle ( 45%-55%)  as well as frequency accuracy (+/-100 ppm) ? Any difference if you use a crystal osc at XTI and XTO instead of your master clk?

    I will be out of office until next week due to holidays in US  but if you go through above suggestions and still have issue with the part,   I will come back to this  next week.

    Regards,

    Arash

  • +1 in reply to Arash Loloee
    Prodigy 10 points

    Hello Arash,

    Thank you for your reply.

    We followed your troubleshooting steps, which led us to identify an issue with the XODIS bit in register 40h when attempting to buffer the XTI clock. We realized that the OSC was powered down, preventing us from decoding the SPDIF input at 192kHz. However, we managed to generate the output signals at 192kHz by clearing the XODIS bit.

    Thank you very much for your support!

    Best regards.

    Felipe Delgado