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TLV320AIC3253: Digital microphone configuration - Right channel outputs noise.

Annaprabu R
Prodigy 10 points
Part Number: TLV320AIC3253

Tool/software:

Dear TI Team,

We are experiencing an issue with the TLV320AIC3253 audio codec in a digital microphone configuration. The setup utilizes two microphones in stereo mode (left and right channels), but we are encountering a problem with the right channel.

Configuration details are as follows:
-----------------------------------------------
    Sample Rate (WCLK): 16 kHz
    Bit Clock (BCLK): 512 kHz
    Master Clock (MCLK): 12.40 MHz

Observations indicate that the left channel outputs proper sound, while the right channel outputs noise. Furthermore, probing the WCLK and DOUT signals from the audio codec reveals that the left channel outputs proper data as expected, whereas the right channel outputs repeated data, resulting in noise during playback.
We have attached the configuration settings and a probed signal image for your reference. Could you please assist us in identifying and resolving this issue?

Note: We have also verified the issue with different sample rates (8 kHz, 24 kHz, and 48 kHz), but the results remain the same.

Thanks in advance!

Regards,
Annaprabu

16Khz_configuration.txt 
 ###############################################
 #
 # Digital Microphone Script
 #
 ###############################################
 ###############################################
 # Software Reset
 ###############################################
 #
 # Select Page 0
 w 30 00 00
 #
 # Initialize the device through software reset
 w 30 01 01
 #
 ###############################################
 ###############################################
 # Clock and Interface Settings
 #--------------------------------------------
# The codec receives: MCLK = 12.40 MHz,
 # WCLK = 16 kHz
 ###############################################
 #
 # Select Page 0
 w 30 00 00
 #
 # PLL_clkin = MCLK, codec_clkin = PLL_CLK,
 # PLL on, P=1, R=1, J=5, D=2820
 w 30 04 03 91 05 0B 04
 #
 # NADC = 2, MADC = 16, dividers powered on
 w 30 12 82 90
 #
 # AOSR = 128
 w 30 14 80
 #
 ###############################################
 ###############################################
 # Configure Power Supplies
 ###############################################
 #
 # Select Page 1
 w 30 00 01
 #
 # Disable weak AVDD in presence of external
 # AVDD supply
 w 30 01 08
 #
 # Enable Master Analog Power Control
 w 30 02 00
 #
 # Set the REF charging time to 40ms
 w 30 7b 01
 #
 ###############################################
 ###############################################
 # Configure Processing Blocks
 ###############################################
 #
 # Select Page 0
 w 30 00 00
 #
 # PRB_R2 selected
 w 30 3D 02
 #
 ################################################
 # High-pass first order Butterworth2 filter,
 # fc = 80 Hz
 ###############################################
 #
 # Write to Buffer A:
 #
 # BIQUAD A, Left Channel (Page 8, Register 36, C7-C11)
 w 30 00 08
 w 30 24 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
 #
 # BIQUAD A, Right Channel (Page 9, Register 44, C39-C43)
 w 30 00 09
 w 30 2c 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
 #
 ###############################################
 ###############################################
 # Configure ADC Channel
 ###############################################
 #
 # Select Page 0
 w 30 00 00
 #
 # Configure MISO as clock output for DIGMIC
 w 30 37 0E
 #
 # LADC and RADC enabled for DIGMIC
 # Route SCLK as DIGMIC_DATA
 # Power up LADC/RADC
 w 30 51 DC
 #
 # Unmute LADC/RADC
 w 30 52 00
 #
 ###############################################
 # Volume Up LADC
 w 30 53 28
 # Volume Up RADC
 w 30 54 28

  • 0
    TI__Mastermind 32955 points

    Hi Annaprabu,

    Your script seems nearly identical to a working script from a different e2e thread, so it it probably not a script issue.

    Can you confirm that your two digital mics are latched on different edges? Your left channel should be latched to the rising edge, while the right channel is latched to the falling edge of the PDM Clock. Digital mics should have an edge alignment pin that allows you to select which edge the mic latches to.

    Best regards,
    Jeff McPherson