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PCM6020-Q1: I2C setting about BCLK_POL

Youhei Miyaoka
Expert 4555 points
Part Number: PCM6020-Q1


Tool/software:

Hi team,

BCLK_POL is the second bit of Register0x07. When this IC is used as a Slave, is it correct to shift the timing of the Data to BCLK by setting this register, not to change the polarity of the BCLK input/output to fsync?

In addition, Figure 24/27 in the Datasheet has inverted polarity. Is this correct understanding correct as a diagram of the clock when this IC is used as a Master?

Regards,

Youhei MIYAOKA

  • 0
    TI__Mastermind 27710 points

    Hi Youhei,

    Yes, the timing diagram is the same in both target and controller mode. When BCLK_POL = 0 (default) the output data latches onto the synchronized rising edge of BCLK and FSYNC. When BCLK_POL= 1, the data will latch onto the rising edge of FSYNC and falling edge of BCLK. 

    In Target mode, the Audio format that the host provides will help you determine whether to inverse the polarity of BCLK. Both the host format and ADC register configuration must be aligned.