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TLV320AIC3109-Q1: Audio Data Serial Interface Timing Requirements

Part Number: TLV320AIC3109-Q1

Tool/software:

Dear Team,

My customer is evaluating the 6PAIC3109TRHBRQ1 (TLV320AIC3109-Q1) on their system. They want to confirm the rise/fall time requirements described in “6.6 Audio Data Serial Interface Timing Requirements” in the data sheet.

For the applicable range of  rise/fail time;
Q1: Unlike other items, BCLK or others are not specified, but are you aware that BCLK, WS, DI, DO are the target if this rise/fall time?

About rise/fail time 4ns;
Q2: On their system board currently under evaluation, the rise time and fall time are measured at 10% and 90% of the waveform, respectively, and the time is about 4.7 ns. On the data sheet, it is specified as 4ns (max), so please provide information such as "is it out of range?" or the measurement method is different (is it other regulation not 0%-90%?).

Best Regards,

Koshi Ninomiya

  • Hi Ninomiya-san,

    1) Yes the rise and fall times apply to all BCLK, WS, DI, and DO.

    2) The definition of high and low is actually 70% and 30% based on the logic level spec below: 

    So by measuring from 30% to 70% rather than 0% to 90%, your rise time may improve and fall below 4ns.

    Best regards,
    Jeff McPherson