Tool/software:
Hello,
I have read the TLV320AIC3107 datasheet power sequencing section, which mentions the constraints on IOVDD, AVDD, DRVDD, and DVDD. I have also read a bunch of forum posts here explaining why certain of those constraints exist. However, I have not seen any stated requirement on SPVDD. Would it be acceptable, for example, to have SPVDD come up tens of milliseconds before IOVDD?
Also, let's say I put a switch on DVDD (which is supposed to come up last) but not IOVDD (which is supposed to come up first). Would it be okay for the chip to have IOVDD up and all other rails down, for an indefinite period of time, until I wanted to switch on all the rails other than IOVDD?
Thanks!