TLV320AIC3268: TLV320AIC3268 clock domain

Part Number: TLV320AIC3268

Tool/software:

Hello everyone,

i'm wondering if the TLV320AIC3268 is able for this setup : 

DAC Fs = ADC Fs = 48Khz, (MCLK = 12.288Mhz ; PLL_CLK = 98.304 Mhz ; ADC_CLK = DAC_CLK = 49152Khz)

  • ASI1 = I2S 16 bits - Master with WCLK = 48Khz
  • ASI2 = I2S 16 bits - Master with WCLK = 16Khz (down sampling thanks to the WCLK and BCLK divider)
  • ASI3 = I2S 16 bits - Slave with WCLK = 8Khz (how can it be done? as the WCLK divider seems to be available only if ASI is master)

the sample rate of the miniDSP is 48Khz and is in charge to mix the 3 x ASI.

Do i need a ASRC for such configuration ?

Thank you for your help

Sebastien

  • Hi Sebastien,

    If ASI3 is a slave, then WCLK and BCLK must be provided to the codec from some other host.

    That 48kHz number that PPS is showing you is actually the sample rate of the USB controller providing clocks to the codec (for slave mode). The DSP will run on CLKIN / N:

    Since all 3 sample rates are integer multiples, I don't think an ASRC will be necessary.

    Best regards,
    Jeff McPherson

  • Hello Jeff,

    thank you for your answer.

    There is something unclear for me : 

    (just for your understanding, i'm not using the eval kit but our own design)

    To help to identify the settings and register, we use Codec Control for the 3262.

    here is the screenshot of our configuration : 

    do we agree that the sampling frequency of the ASI3 does not correspond to the sampling frequency of the miniDSP?

    The problem does not occur for ASI2 (WCLK operating at 16Khz) as we can use the WCLK divider to reduce sampling from 48KHz to 16Khz.


    Am I missing something?

  • Hi Sebastien,

    When you say "the problem does not occur" what do you mean? Are you testing the configuration on your custom board?

    Whichever pin you have programmed as WCLK3 and BCLK3 should be where your master is sending the clocks to.

    Best regards,
    Jeff McPherson