TLV320AIC3268: TLV320AIC3268 clock domain

Hello Jeff,

thank you for your answer.

There is something unclear for me : 

(just for your understanding, i'm not using the eval kit but our own design)

To help to identify the settings and register, we use Codec Control for the 3262.

here is the screenshot of our configuration : 

do we agree that the sampling frequency of the ASI3 does not correspond to the sampling frequency of the miniDSP?

The problem does not occur for ASI2 (WCLK operating at 16Khz) as we can use the WCLK divider to reduce sampling from 48KHz to 16Khz.

Am I missing something?

Hi Sebastien,

When you say "the problem does not occur" what do you mean? Are you testing the configuration on your custom board?

Whichever pin you have programmed as WCLK3 and BCLK3 should be where your master is sending the clocks to.

Best regards,
Jeff McPherson

Hello Jeff,

sorry for my long silence (I've been busy with another project)

let me explain it again : 

i'm trying to run the ADC/DAC at a sample Rate of 48Khz (i would accept 16k or 32k but for the example below, let's assume 48Khz).

ASI1 is master, interfaced with a slave in I2S with WCLK = 16Khz. Thanks to the WCLK divider B0_P4_R13, i'm able to match the 16Khz

ASI2 is master, very similar than above

ASI3 is slave, the master provides I2S with WCLK = 8Khz. (WCLK3 and BCLK3 are input)

• Can you confirm WCLK divider is only available if the 3268 is master (WCLK/BCLK are output) ?
• How can I sync the signal enerting on ASI3, which runs at 8Khz, while the DAC/ADC runs at 48Khz?

Hi Sebastien,

Correct, WCLK divider is only available in master mode, it only goes in one direction.

If you WCLK coming into the codec in slave mode is 8kHz, you can't run the ADC/DAC at an effective 48kHz. You would need to adjust the clock tree to accommodate the new ratio

Best regards,
Jeff McPherson

Hi Jeff,

thank you, it's clear.

and if WCLK going out of the codec in master mode at 8Khz, can i run the ADC/DAC at 48Khz.

i did some test, and i do not understand why it's not working properly : 

• MICPGA of the TLV3268-> ADC@48Khz -> miniDSP ->ASI3@8Khz -> I2S stream to slave : audio is OK, no distorsion, good audio bandwitdh.
• I2S stream from slave -> ASI3@8Khz -> miniDSP -> DAC@48KHz -> HPR/L of the TLV3268 : audio is crackling (as if the sampling frequency were wrong)

if the ADC/DAC runs at 8khz (insteaf of 48khz), everything works fine.

thank you

Hi Sebastien,

If the WCLK leaving the codec is 8kHz then you can't run the ADC/DAC at 48kHz. The oversampling ratio would be mismatched. This is likely the reasoning of your crackling sound. There should be a sample rate converter block in PPS that you can use to take in the data at 8kHz but process it at 48k.

Best regards,

Jeff McPherson

Jeff McPherson said:

There should be a sample rate converter block in PPS

Does the 3268 have SRC ? to me the 3262 has but not the 3268.

Is there any block to manage this ?

Hi Sebastien,

Sorry I was mistaken. You were right the AIC3262 supports an ASRC but the 3268 doesn't and there isn't a block for this. 

I do wonder though what the advantage of up sampling would be. You would not gain any audio quality by up sampling since the audio data would still be limited to the 8k Nyquist rate anyway. As you mentioned, the flow works if you run at 8kHz. IF your host is limited to 8kHz then your DAC output will limited as well, even if you artificially increase the sample rate. 

Best regards,
Jeff McPherson

Hello Jeff,

but i also have other serial audio on ASI1 and ASI2 running at 48Khz, so i didn't want to downgrade the audio quality of the other sources

Hi Sebastien,

Only 1 ASI can be used at a time so I don't think there's a concern about downgrading the other sources. When you use ASI1 and ASI2 you can return to 48kHz.

Hello Jeff,

What do you mean by "Only 1 ASI can be used at a time", as my ProcessFlow is a kind of ASI mixer. I do not understand your answer.

Hi Sebastien,

Sorry disregard that statement. I see better what you're trying to do.

I am also realizing I misread your earlier statement and everything seems to work when going down from 48kHz to 8kHz but not the other way around.

I'm still suspicious that the DSP will not be able to handle mixed sample rates well since PPS specifies the sample rate of the DSP like you are showing and the DSP also runs on a particular clock per the clock tree. Since there is no SRC I don't think the mixing will be reliable. 

Have you checked that there are no issues coming from the I2S stream using some kind of external monitor or loopback. Just to confirm that the issue is codec related? 

Best regards,
Jeff McPherson