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TLV320ADC3140: Clocking Tolerance

Part Number: TLV320ADC3140


Tool/software:

We are working on a project utilizing the tlv320adc3140.  We want to run it in ASI master mode and provide the MCLK across the GPIO1 pin.  We want to provide a 20MHz clock out of the MCU into the 3140.  However, this frequency is about 1.5% greater than the 19.68MHz that is listed as one of the "target" frequencies. The questions is this: Are there any issues that may arise due to using the MCU frequency of 20MHz while using the dividing ratios that are suggested for a 19.68MHz clock?