TLV320ADC6140: Cannot get 48KHz FCLK output in mater mode

Robert Basil

Part Number: TLV320ADC6140

Tool/software:

I am trying to configure the TLV320ADC6140 as a master, outputting FCLK @ 48KHz and BCLK @ 3.072MHz (x64) on an I2S output.
1 - I looked in the datasheet and did not see that I had to use an MCLK input, but I am guessing I do in master mode. Can someone confirm this?
2 - If I use the TI eval PCB and SW for this device and wire the I2C to configure my device, I see FCLK = 46.2KHz and the PLL config shows it should be 96KHz (photo below). I am not sure what to do at this point. Any suggestions or questions that might help understand this and help me get the 48KHz FCLK I desire. As noted in the photo, my MCLK is external at 12MHz.

8 months ago

0 Daveon Douglas 8 months ago

TI__Mastermind 27410 points

Hi Robert,

Here is an article that explains how to configure the device is master mode: Configuring and Operating TLV320ADCx140 as Audio Bus Master

MCLK is required in master mode, provided through the GPIO pin. 48kHz FSYNC and a 3.072MHz BLCK output is supported and can be configured through the MST_CFG0 and MST_CFG1 register.

The tool you're using is to manually configure the PLL during master mode and is only required to generate non-standard audio sampling rates.

0 Robert Basil 8 months ago in reply to Daveon Douglas

Prodigy 60 points

Hi Daveon,

Thanks for the manual. I used the config tool to directly control my ADC and could not get anything logical. With the manual, there were 4 registers that I needed to update and all good. Thanks again.

Best
Rob

Audio

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TLV320ADC6140: Cannot get 48KHz FCLK output in mater mode