TLV320AIC3263EVM-U: TLV320AIC3263

Hello,

w 30 7f 00 # Select Book 0
w 30 00 01 # Select Page 1
w 30 34 54 # LEFT mic selection control IN1L IN2L IN3L RIN = 10k
w 30 36 14 # CM1 not selection IN2R IN3R Selected RIN = 10k
w 30 3b 32 # mic PGA Left +25dB
w 30 1f 0e # HPL +14dB
w 30 20 0e # HPR +14dB
w 30 3d 00 # PTM_R4 LEFT ADCPGA RIGHT ADC PGA

w 30 00 00 # Select Page 0
w 30 51 c0 # LEFT/RIGHT ch ADC power up
w 30 52 00 # LEFT/RIGHT ADC ch unmute

Hello,

Yesterday, I had already added these registers, but I forgot to mention them in the forum. Below is my current configuration:

• I can receive audio from the microphone on ASI1 and hear it through the headphones.
• I can hear audio through the headphones from ASI2.
• However, when I speak into the microphone, I do not see any signal on the ASI2 DOUT pin.
• I verified this using a logic analyzer, but there is no activity on ASI2 DOUT.

I also examined the word clock and bit clock of the modem connected to ASI2 using a logic analyzer, and they appear to be within the correct range:

• BCLK = 2 MHz
• WCLK = 8 kHz

While I can successfully receive audio on the DOUT pin of ASI1, I cannot receive any audio on ASI2's DOUT pin, and I am unable to determine the cause.

I would appreciate any help you can provide.

Best regards,

Ayşe YILMAZ

ayse yilmaz said:

While I can successfully receive audio on the DOUT pin of ASI1, I cannot receive any audio on ASI2's DOUT pin, and I am unable to determine the cause.

What I meant here is that I cannot see the audio output from the microphone on ASI2 using the logic analyzer

Hi Ayse,

Are you clock settings between the ADC and DAC symmetrical? From the code they look different. One possible cause of the DOUT not toggling is there is a clock error. Even though it works on the DAC side, if the ADC has a different clock configuration there may be issues.

Another debugging step would be to swap the hardware connections of ASI1 and ASI2 and see if the issue follows.

Best regards,
Jeff McPherson

Hi Jeff,

I configured the clocks through the codec control interface and calculated them using TI's clock calculator, as shown in the attached images.

Both DAC_fs and ADC_fs are set to 8 kHz.

The issue still remains.
Could you help identify if there is any mistake in the clock configuration?

The CFG file generated by PurePath Studio is also attached for reference.

base_main_Rate8.cfg

I have another question that is confusing me:

If I need to receive and transmit audio at different sample rates using different SAI interfaces,
which interface should the ADC and DAC clocks (ADC_fs and DAC_fs) be aligned with?

How should I configure the codec clocks when using multiple audio streams with different rates?

Best regards,

Ayşe YILMAZ

Hi Ayse,

Why the different AOSR and DOSR rates? What happens if you adjust the dividers such that AOSR equals 768? Your clocking seems to meet all the conditions otherwise.

One other thing to try to simplify the test is remove the spliter and biquad from the process flow. Just do a simple Dec in -> I2S out

Regarding different samples rates, the DAC can use an ASRC to handle different sample rates on the playback side (receiving different sample rate data on the I2S inputs), but it cannot do so for the recording side. Whichever device needs to do the recording, the ADC should be following the sample requirements of that device.

Best regards,
Jeff McPherson

Hi Jeff,

I adjusted the clocks based on example 6.3 from the following link:
https://www.ti.com/tool/download/SLAC598

In that example, the clock input is 4 MHz, and the clock source is MCLK.
Since I have 2 MHz PCM, I wanted to derive the clock source from BCLK instead of MCLK.

Based on this, I made adjustments and achieved 8 kHz as the target sampling rate.
I also set DOSR to 128 and MDAC to 48, so now I believe the configuration is symmetric.

Do you see any issue with this approach?

Registers

w 30 7f 00 # Select Book 0
w 30 00 00 # Select Page 0

w 30 05 10 # PLL source BCLK2
w 30 06 92 # R=2 J=24 D=0 P=1 PLL power up DIV=1
w 30 07 18 # R=2 J=24 D=0 P=1 PLL power up DIV=1
w 30 08 00 # R=2 J=24 D=0 P=1 PLL power up DIV=1
w 30 09 00 # R=2 J=24 D=0 P=1 PLL power up DIV=1
w 30 0a 01 # R=2 J=24 D=0 P=1 PLL power up DIV=1
w 30 04 33 # ADC and DAC source PLL_CLK
w 30 12 82 # ADC_CLK_pwr NADC = 2
w 30 13 b0 # ADC_M_CLK_pwr MADC = 48 AOSR = 128
w 30 14 80 # AOSR = 128
w 30 0b 82 # NDAC = 2 power up
w 30 0c b0 # MDAC = 48 power up
w 30 0d 00 # DOSR 128
w 30 0e 80 # DOSR 128

Additionally, I simplified my PurePath setup for testing purposes to eliminate other variables, but I still do not see any data on ASI2 DOUT.

Do you see any issue with this approach, or anything else I should check?

Best regards,

Ayşe YILMAZ

Hi Ayse,

Thank you. Does the headphone output still work on ASI2 in this new configuration?

An additional test is to check that the PLL is actually running with the clock input. You can route the PLL output clock onto a GPIO pin and double check that the output frequency is correct.

If there is no output, double check the function of CLKOUT by testing something known like BCLK1.

Best regards,
Jeff McPherson

Hi Jeff,

Yes, in this configuration, the headphone output on ASI2 is still working properly. We haven't made any changes that would affect the headphone path.

Regarding the PLL output test, this will require additional time. The codec is implemented on our custom SoM design, and the GPIO pins are not brought out to test points or connectors. Our hardware team is working on manually wiring out the necessary GPIOs for testing, but this process may take some time.

Additionally, since ASI1 is internally connected to the CPU on the SoM, re-routing ASI1 BCLK to a modem for testing is not feasible in the current hardware setup.

Since ASI2 and ASI3 pins are exposed on the SoM, I can monitor their activity using a logic analyzer.

Best regards,
Ayşe YILMAZ

Hi Jeff,

First of all, I have implemented all the configurations I mentioned earlier in this thread on the TLV320AIC3263EVM-U, and I monitored GPIO1 using a logic analyzer.

• When I routed ASI2 ADC BCLK out to GPIO1, I observed a signal stuck high, as shown in the attached image.
• When I routed ASI2 ADC WCLK out to GPIO1, I observed a stable 8 kHz signal.

Could there be a mistake in my configuration that is causing this behavior?
Also, could this be the reason why I cannot receive audio from the microphone through ASI2?

Thank you for your support.

This is the configuration I used to route these signals to GPIO1. Could you confirm if this routing is correct?

Best regards,
Ayşe YILMAZ

Hi Ayse,

You could double check with ASI1 as well since that is known to work. I'm assuming that just by changing GPIO1 you get the 8kHz signal you described.

I did notice at the top of your thread you mention ASI is master mode. Is the master clock connected to BCLK2? Based on your settings BCLK2 (PLL input) should've been passed onto GPIO1

Best regards,
Jeff McPherson

Hi,

When I configure the EVM as follows for ASI2, everything works correctly for ASI2:

• DAC miniDSP DIn 1 → ASI2 Data Out

• ADC Input → miniDSP_A Dout 1

In this setup, when I connect the modem to ASI2, I can both receive and transmit audio successfully.

However, when I try the following configuration, it doesn't seem to work:

• DAC miniDSP DIn 1 → ASI1 Data Out

• DAC miniDSP DIn 2 → ASI2 Data Out

• DAC miniDSP DIn 3 → ASI3 Data Out

And:

• ADC Input 1 → miniDSP_A Dout 1

• ADC Input 2 → miniDSP_A Dout 2

• ADC Input 3 → miniDSP_A Dout 3

Is there any limitation or specific configuration required when using multiple ASI outputs and multiple ADC paths simultaneously?

Thank you for your support.

Hi Ayse,

In this configuration I believe ASI2 is providing data for both DAC1 and DAC2 I2S inputs. Does the process flow match this as well? In1 -> Out2

Thanks,
Jeff McPherson