• State
  • Replies 8 replies
  • Subscribers 30 subscribers
  • Views 131 views
  • Users 2 members are here
Support feedback
Options
Options
Similar topics

TLV320ADC3101: output frequency is doubled and have noise

cayden liu
Intellectual 1206 points
Part Number: TLV320ADC3101

Tool/software:

Hi TI,

I use TLV320ADC3101 develop project now, below is my schematic:

I2S mode, MCLK=12.288M fs=48k BCLK=1.536M, 16 bits

My register configuration is as follows:

I2CWRITE(I2C_ADC31, 0, 0X0);
I2CWRITE(I2C_ADC31, 1, 0X01);

I2CWRITE(I2C_ADC31, 4, 0X03);//use PLL
I2CWRITE(I2C_ADC31, 5, 0X91);//P R
I2CWRITE(I2C_ADC31, 6, 0X01);//J
I2CWRITE(I2C_ADC31, 7, 0X00);//D MSB
I2CWRITE(I2C_ADC31, 8, 0X00);//D LSB
I2CWRITE(I2C_ADC31, 18, 0X81);//NADC
I2CWRITE(I2C_ADC31, 19, 0X82);//MADC
I2CWRITE(I2C_ADC31, 20, 0X80);//AOSRS
I2CWRITE(I2C_ADC31, 27, 0X00);
I2CWRITE(I2C_ADC31, 61, 0X01);
// Set register ------------------------->page 1
I2CWRITE(I2C_ADC31, 0, 0X01);
I2CWRITE(I2C_ADC31, 51, 0X0);
I2CWRITE(I2C_ADC31, 59, 0X0);
I2CWRITE(I2C_ADC31, 60, 0X0);
I2CWRITE(I2C_ADC31, 52, 0XFC);
I2CWRITE(I2C_ADC31, 55, 0XFC);

// Set register ------------------------->page 0
I2CWRITE(I2C_ADC31, 0, 0X0);
I2CWRITE(I2C_ADC31, 81, 0XC2);
I2CWRITE(I2C_ADC31, 82, 0X0);

I2CWRITE(I2C_ADC31, 83, 0X0);
I2CWRITE(I2C_ADC31, 84, 0X0);

There are two issue:

1.When a 1 kHz positive wave is input, the output becomes 2 kHz. And there is interference from other frequency bands.

2.There is a noise signal of about 25db, and the frequency is about 45Hz-100Hz when I didn`t give input,

Would you like share some suggest to help us solve this problem?

BR

Cayden

  • 0
    TI__Expert 6370 points

    Hi Cayden,

    Can you measure your I2S clocks on a scope? Let's make sure they are not out of sync, and if you can measure your digital signal output on a scope in comparison that will help too. Another thing I noticed from your schematic is that you will want all power supplies to have a 1uF decoupling capacitor in parallel with the 0.1uF capacitor. And, one more thing is that you may not need the 22ohm resistors on your I2S lines unless they are very long, I think this is likely not your problem but maybe you could replace them with 0ohm to see if it makes a difference. Let me know about the scope shots of the I2S.

    Best,
    Mir

  • 0
    Prodigy 45 points

    The first issue is that when a 1kHz positive wave is input, the output becomes 2kHz, which has been resolved。 The reason is that single channel data was used as dual channel data。

    The issue of noise still needs to be addressed。

  • 0 in reply to Mir Jeffres
    Prodigy 45 points

    Hello, could we ask if we are ok to contact with you by emails? We now got the urgent issue, clients already sold the models, now waiting for our solution. We are wondering maybe emails would be more convenience. Thank you so much! 

  • 0 in reply to user5360300
    TI__Expert 6370 points

    Hi,

    You can, or we can keep going on here. Please accept my friend request so I can send you my email. Can you send more info about your input signal, can you measure the input on a scope and compare to the digital output? Also, can you send scope shots of the I2S clocks/data?

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 45 points

    HI,These are scope shots.Please take a look.

  • 0 in reply to user5360300
    TI__Expert 6370 points

    Hi,

    Have you tried adding the 1uF decoupling capacitors on all VDD inputs? Also, can you change the register 5 on page 0 to 0x11 to turn off the PLL, since it is not used? Then you will also need to change register 4 to 0x00 to set the input to the dividers as MCLK and not the PLL_CLK. 

    Let me know when you have tried this register change, and if you could give a register dump if this is not working that would be helpful to figure out what is going wrong. The clocks look okay, but a bit noisy and this may also be causing issues.

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 45 points
    Hi ,

    I've tried changing the register settings as you suggested. Here are the details:
    1. I've changed register 5 on page 0 to 0x11 to turn off the PLL and register 4 to 0x00 to set the input to the dividers as MCLK.

    However, the issue still persists. Here is the register dump for your reference:

    I hope this information helps you figure out what's going wrong. If you need any other information or further testing, please let me know.
  • 0 in reply to user5360300
    TI__Expert 6370 points

    Hi,

    I noticed in your register dump that register 18, NADC is set to 0x88 instead of 81, meaning your NADC divider is = 8 which is not what you want, you would want it to be 1. Also, just to make sure, your BCLK and WCLK are inputs? Or outputs? Right now the device is configured for them to be inputs (register 27). You may also want to set register 30 to 0x81 if the BCLK is an output, not an input. 

    Also, please see if you can add those decoupling caps in your power circuit, it may help with the noise.

    Best,
    Mir