TLV320AIC3100: test tone

Thanks for the quick response.

The answer is clear—I first need to set up the I2S interface.

I have another question: every time I change a setting in the CodeControl tool, I always get the same initialization script. I haven't yet figured out what is going wrong.

Hi Matthias,

The initialization script is fixed. If you want to generate a script based on your settings, first open the View -> Command window and check "Record." Now all actions you take in the GUI will be recorded in the command buffer. This will create your script in real time. Be sure to use the init script as a reference so that all pieces are taken care of: clocking, input and output routing, gain setting, unmute, etc.

Best regards,
Jeff McPherson

hey,

i have don different test.
first i was chekcing the BCLK and WCLK there before changing the start init de line keep on ground level.
the moment you change them of output to input de line keep on VCC.
info register setting:
page 0
w 30 1b 08
w 30 1b 0c

if you delever de bclk and wclk to the audio codex without a Mclk do you need configur de internal clock gen module?
becose every setting i change i have no respons in the command window.

I find also a strange behaver.

every time you go in digital audio proccessing serial interface en go out and you change notting you git some change for the registers.

Best regard

Matthias,

Hi Matthias,

The GUI is telling you that your clocking set up is not possible. That is why the clocks are at VCC level because the driver is active but there is no signal.

An MCLK is not required, but BCLK must be the input clock source. This spreadsheet calculator gives you the limitations you must follow and help you double check: https://www.ti.com/tool/download/SLAR163

Best regards,
Jeff McPherson

Hi jeff,

i have don dubbel checking and ik do'nt get a bclk and wclk out of the audio codex.

the input on MCLK is 10Mhz.

if i folow the instruction of the config tool i don't get the signals out.
i even get een sugestion to change registers that  you can not change.

i have condole output in the code that it is possibel toe foloow

START: AudioCodec_SelectPage
WRITE: Register 0x00 <- 0x00

READ: Register 0x00 -> 0x00
STOP: AudioCodec_SelectPage
START: AudioCodec_Reset
WRITE: Register 0x01 <- 0x01
READ: Register 0x01 -> 0x00
FAIL: Page 0 - Software reset (Register 0x01 <- 0x01, gelezen: 0x00)

STOP: AudioCodec_Reset
START: AudioCodec_ConfigurePLL
WRITE MULTI: Start Register 0x04, 5 bytes
READ MULTIPLE: [0x04 -> 0x03] [0x05 -> 0x91] [0x06 -> 0x08] [0x07 -> 0x0B] [0x08 -> 0x80]
STOP: AudioCodec_ConfigurePLL
START: AudioCodec_ConfigureAudioFormat
WRITE: Register 0x1B <- 0x00
READ: Register 0x1B -> 0x00
STOP: AudioCodec_ConfigureAudioFormat
START: AudioCodec_ConfigureDirectionSignals
WRITE: Register 0x20 <- 0x02
READ: Register 0x20 -> 0x02
WRITE: Register 0x21 <- 0x03
READ: Register 0x21 -> 0x03
STOP: AudioCodec_ConfigureDirectionSignals
START: AudioCodec_ConfigureDAC
WRITE MULTI: Start Register 0x0B, 6 bytes
READ MULTIPLE: [0x0B -> 0x83] [0x0C -> 0x9B] [0x0D -> 0x00] [0x0E -> 0x80] [0x0F -> 0x20] [0x10 -> 0x04]
STOP: AudioCodec_ConfigureDAC
START: AudioCodec_ConfigureDOSR
WRITE MULTI: Start Register 0x12, 4 bytes
READ MULTIPLE: [0x12 -> 0x83] [0x13 -> 0x9B] [0x14 -> 0x00] [0x15 -> 0x80]
WRITE: Register 0x16 <- 0x20
READ: Register 0x16 -> 0x00
FAIL: biijkomende instellng (Register 0x16 <- 0x20, gelezen: 0x00)

WRITE: Register 0x17 <- 0x04
READ: Register 0x17 -> 0x00
FAIL: biijkomende instellng (Register 0x17 <- 0x04, gelezen: 0x00)

STOP: AudioCodec_ConfigureDOSR
START: AudioCodec_ConfigureDACVolume
WRITE: Register 0x74 <- 0x00
READ: Register 0x74 -> 0x00
WRITE: Register 0x44 <- 0x00
READ: Register 0x44 -> 0x00
WRITE MULTI: Start Register 0x41, 2 bytes
READ MULTIPLE: [0x41 -> 0x00] [0x42 -> 0x00]
STOP: AudioCodec_ConfigureDACVolume
START: AudioCodec_SelectPage
WRITE: Register 0x00 <- 0x01
READ: Register 0x00 -> 0x01
STOP: AudioCodec_SelectPage
START: AudioCodec_ConfigureHeadphone
WRITE: Register 0x21 <- 0x4E
READ: Register 0x21 -> 0x4E
WRITE: Register 0x1F <- 0xC6
READ: Register 0x1F -> 0xC6
WRITE: Register 0x23 <- 0x44
READ: Register 0x23 -> 0x44
WRITE MULTI: Start Register 0x28, 2 bytes
READ MULTIPLE: [0x28 -> 0x0E] [0x29 -> 0x0E]
WRITE: Register 0x24 <- 0x00
READ: Register 0x24 -> 0x00
WRITE: Register 0x25 <- 0x00
READ: Register 0x25 -> 0x00
STOP: AudioCodec_ConfigureHeadphone
START: AudioCodec_ConfigureMIC
WRITE: Register 0x2E <- 0x0B
READ: Register 0x2E -> 0x0B
WRITE MULTI: Start Register 0x30, 2 bytes
READ MULTIPLE: [0x30 -> 0x40] [0x31 -> 0x40]
STOP: AudioCodec_ConfigureMIC
START: AudioCodec_SelectPage
WRITE: Register 0x00 <- 0x00
READ: Register 0x00 -> 0x00
STOP: AudioCodec_SelectPage
START: AudioCodec_ConfigureDSPMode
WRITE: Register 0x3C <- 0x0B
READ: Register 0x3C -> 0x0B
WRITE: Register 0x00 <- 0x08
READ: Register 0x00 -> 0x08
WRITE: Register 0x01 <- 0x04
READ: Register 0x01 -> 0x04
WRITE: Register 0x00 <- 0x00
READ: Register 0x00 -> 0x00
STOP: AudioCodec_ConfigureDSPMode
START: AudioCodec_EnableDAC
WRITE MULTI: Start Register 0x3F, 2 bytes
READ MULTIPLE: [0x3F -> 0xD6] [0x40 -> 0x00]
STOP: AudioCodec_EnableDAC
START: AudioCodec_EnableADC
WRITE MULTI: Start Register 0x51, 2 bytes
READ MULTIPLE: [0x51 -> 0x80] [0x52 -> 0x00]
STOP: AudioCodec_EnableADC
START: AudioCodec_SelectPage
WRITE: Register 0x00 <- 0x01
READ: Register 0x00 -> 0x01
STOP: AudioCodec_SelectPage
START: AudioCodec_ConfigureDSPMode
WRITE: Register 0x2A <- 0x1C
READ: Register 0x2A -> 0x1C
WRITE: Register 0x2B <- 0x1C
READ: Register 0x2B -> 0x1C
WRITE: Register 0x20 <- 0xC6
READ: Register 0x20 -> 0xC6
START: AudioCodec_ConfigureDSPMode
START: AudioCodec_SelectPage
WRITE: Register 0x00 <- 0x00
READ: Register 0x00 -> 0x00
STOP: AudioCodec_SelectPage
Audio Codec Initialized.

best regard
Matthias

Hi,

Our codec expert is out of office until Tuesday. Please be patient as responses will be delayed

Hi Jeff,

Thanks again for your help.

After adjusting the value, the line rises, but there is still no clock signal visible on the scope.

START: AudioCodec_ConfigureAudioFormat direction bcl en wclk
WRITE: Register 0x1B <- 0x0C
READ: Register 0x1B -> 0x0C
STOP: AudioCodec_ConfigureAudioFormat direction bcl en wclk

i need always the wclk en bclk signals because i  use the din en dout.

Just for your information, the tool provides wrong settings. if you look to de din pin you need to change the direction of bclk en wclk in the same way. visueal thats wrong.

best regards,

Matthias

Hi Matthias,

Yes the GUI does have the direction backwards. What are the most recent settings you're using in the clock gen module calculator tool? Your BCLK may have been too low before.

Best regards,
Jeff McPherson

hey Jeff,

this moment ik use a 10Mhz ( had the parts for this) clock for de MCLK (i now its better 12,2888 Mhz for less jitter).
clock is stable tested witch the scope an also check it stable on de MCLK pin of the chip itself.

sample rate 8Kz (16bit i2s).

START: AudioCodec_ConfigurePLL
WRITE MULTI: Start Register 0x04, 5 bytes
READ MULTIPLE: [0x04 -> 0x03] [0x05 -> 0x91] [0x06 -> 0x08] [0x07 -> 0x0B] [0x08 -> 0x80]
STOP: AudioCodec_ConfigurePLL
START: AudioCodec_ConfigureAudioFormat direction bcl en wclk
WRITE: Register 0x1B <- 0x0C
READ: Register 0x1B -> 0x0C
STOP: AudioCodec_ConfigureAudioFormat direction bcl en wclk

best regards,
matthias

Hi Matthias,

I'm looping in a colleague to help since I am away from the lab.

Hi Mir,

Could you try this on an EVM since I am travelling? We need to just get a script to get BCLK and WCLK output with a 10MHz MCLK input.

# Set BCLK and WCLK to output
w 30 1b 0c

# PLL P = R = 1, J = 8, D = 2944
w 30 4 03 91 08 0b 80

#NADC = 3
w 30 12 83

#MADC = 27
w 30 13 9b

# AOSR = 128
w 30 14 80

#NDAC = 3
w 30 b 83

#MDAC = 27
w 30 c 9b

#DOSR = 128
w 30 d 00 80

#IDAC = 32
w 30 f 20

#DAC PRB = 4
w 30 10 04

Thanks and Best regards,
Jeff McPherson

Hi,

I've tried several different approaches, but I still haven't figured out how to get the system working.

I'm hoping you can give me a push in the right direction.

Best regards,
Matthias

Hi Matthias,

Today is a holiday for TI in the U.S. so I am away from the lab. I will try this on an EVM next week to give you something that can work.

Best regards,
Jeff McPherson

Hi Matthias,

I've created a script that should get you output clocks. Please apply it and see if it works:

# --------------------------------------------------------------- page 0 is selected
w 30 00 00
# s/w reset
> 01
# PLL_clkin = MCLK,codec_clkin = PLL_CLK
#R = 1, J = 8, D = .4672, P = 1
#NADC/NDAC = 3
#MADC/MDAC = 5
#AOSR = DOSR = 128
#output sample rate of 44.1kHz
w 30 4 03 91 08 12 40
w 30 12 83
w 30 13 85
w 30 14 00 80
w 30 16 20
w 30 17 04
w 30 b 83
w 30 c 85
w 30 d 00 80
w 30 f 20
w 30 10 04
w 30 1b 08
w 30 1b 0c
# DAC => volume control thru pin disable
w 30 74 00
# DAC => drc disable, th and hy
w 30 44 00
# DAC => 0 db gain left
w 30 41 00
# DAC => 0 db gain right
> 00
# --------------------------------------------------------------- page 1 is selected
w 30 00 01
# De-pop, Power on = 800 ms, Step time = 4 ms
w 30 21 4e
# HPL and HPR powered up
w 30 1f c2
# LDAC routed to HPL, RDAC routed to HPR
w 30 23 88
# HPL unmute and gain 1db
w 30 28 0e
# HPR unmute and gain 1db
> 0e
# No attenuation on HP
w 30 24 00
w 30 25 00

# MIC BIAS = AVDD
w 30 2e 0b
# MICPGA P = MIC 10k
w 30 30 40
# MICPGA M - CM 10k
> 40
# --------------------------------------------------------------- page 0 is selected
w 30 00 00
# select DAC DSP mode 11 & enable adaptive filter
w 30 3c 0b
w 30 00 08
w 30 01 04
w 30 00 00
# POWERUP DAC left and right channels (soft step disable)
w 30 3f d6
# UNMUTE DAC left and right channels
> 00
# POWERUP ADC channel
w 30 51 80
# UNMUTE ADC channel
> 00
w 30 00 01
# Unmute Class-D Left
w 30 2a 1c
# Unmute Class-D Right
w 30 2b 1c
# Power-up Class-D drivers
w 30 20 c6

Hey jeff,

i have try the script but there is no wclk an bclk commout. the bclk co of 0 to 1 and stay on 1.




the debug output.
WRITE: Register 0x00 <- 0x00
READ: Register 0x00 -> 0x00
WRITE: Register 0x01 <- 0x01
READ: Register 0x01 -> 0x00
FAIL: Software reset (Register 0x01 <- 0x01, gelezen: 0x00)   => is a normal fail that i need to see els the reset is not ok.

WRITE MULTI: Start Register 0x04, 5 bytes
READ MULTIPLE: [0x04 -> 0x03] [0x05 -> 0x91] [0x06 -> 0x08] [0x07 -> 0x12] [0x08 -> 0x40]
@@@@@WRITE: Register 0x12 <- 0x83
READ: Register 0x12 -> 0x83
WRITE: Register 0x13 <- 0x85
READ: Register 0x13 -> 0x85
WRITE: Register 0x14 <- 0x00
READ: Register 0x14 -> 0x00
WRITE: Register 0x15 <- 0x80
READ: Register 0x15 -> 0x80
WRITE: Register 0x16 <- 0x20
READ: Register 0x16 -> 0x00
FAIL: DOSR LSB (Register 0x16 <- 0x20, gelezen: 0x00)

WRITE: Register 0x17 <- 0x04
READ: Register 0x17 -> 0x00
FAIL: DAC clock enabled (Register 0x17 <- 0x04, gelezen: 0x00)

WRITE: Register 0x0B <- 0x83
READ: Register 0x0B -> 0x83
WRITE: Register 0x0C <- 0x85
READ: Register 0x0C -> 0x85
WRITE: Register 0x0D <- 0x00
READ: Register 0x0D -> 0x00
WRITE: Register 0x0E <- 0x80
READ: Register 0x0E -> 0x80
WRITE: Register 0x0F <- 0x20
READ: Register 0x0F -> 0x20
WRITE: Register 0x10 <- 0x04
READ: Register 0x10 -> 0x04
WRITE: Register 0x1B <- 0x08
READ: Register 0x1B -> 0x08
WRITE: Register 0x1B <- 0x0C
READ: Register 0x1B -> 0x0C
WRITE: Register 0x74 <- 0x00
READ: Register 0x74 -> 0x00
WRITE: Register 0x44 <- 0x00
READ: Register 0x44 -> 0x00
WRITE: Register 0x41 <- 0x00
READ: Register 0x41 -> 0x00
WRITE: Register 0x42 <- 0x00
READ: Register 0x42 -> 0x00
WRITE: Register 0x00 <- 0x01
READ: Register 0x00 -> 0x01
WRITE: Register 0x21 <- 0x4E
READ: Register 0x21 -> 0x4E
WRITE: Register 0x1F <- 0xC2
READ: Register 0x1F -> 0xC6
FAIL: Power up HPL/HPR (Register 0x1F <- 0xC2, gelezen: 0xC6)  => also normal informtiaon tell 1 bit can not be alterd en stay on 1.

WRITE: Register 0x23 <- 0x88
READ: Register 0x23 -> 0x88
WRITE: Register 0x28 <- 0x0E
READ: Register 0x28 -> 0x0E
WRITE: Register 0x29 <- 0x0E
READ: Register 0x29 -> 0x0E
WRITE: Register 0x24 <- 0x00
READ: Register 0x24 -> 0x00
WRITE: Register 0x25 <- 0x00
READ: Register 0x25 -> 0x00
WRITE: Register 0x2E <- 0x0B
READ: Register 0x2E -> 0x0B
WRITE: Register 0x30 <- 0x40
READ: Register 0x30 -> 0x40
WRITE: Register 0x31 <- 0x40
READ: Register 0x31 -> 0x40
WRITE: Register 0x00 <- 0x00
READ: Register 0x00 -> 0x00
WRITE: Register 0x3C <- 0x0B
READ: Register 0x3C -> 0x0B
WRITE: Register 0x00 <- 0x08
READ: Register 0x00 -> 0x08
WRITE: Register 0x01 <- 0x04
READ: Register 0x01 -> 0x04
WRITE: Register 0x00 <- 0x00
READ: Register 0x00 -> 0x00
WRITE: Register 0x3F <- 0xD6
READ: Register 0x3F -> 0xD6
WRITE: Register 0x40 <- 0x00
READ: Register 0x40 -> 0x00
WRITE: Register 0x51 <- 0x80
READ: Register 0x51 -> 0x80
WRITE: Register 0x52 <- 0x00
READ: Register 0x52 -> 0x00
WRITE: Register 0x00 <- 0x01
READ: Register 0x00 -> 0x01
WRITE: Register 0x2A <- 0x1C
READ: Register 0x2A -> 0x1C
WRITE: Register 0x2B <- 0x1C
READ: Register 0x2B -> 0x1C
WRITE: Register 0x20 <- 0xC6
READ: Register 0x20 -> 0xC6

Audio Codec Initialized: 16-bit, 44.1kHz via PLL
Audio Codec Initialized.

after i get no bclk and wclk i added this but was no succes to.

WRITE: Register 0x00 <- 0x00
READ: Register 0x00 -> 0x00
WRITE: Register 0x1D <- 0x04
READ: Register 0x1D -> 0x04

best regard,
Matthias

Hi Matthias,

The software reset "fail" is normal. That bit is self clearing once the reset is complete. But it looks like there are some other errors that are preventing the script from working fully. Are those failing I2C writes being acknowledged?

Thanks,
Jeff McPherson

hey jef,


the fail message is when the readback is not the same like the write.

WRITE: Register 0x01 <- 0x01

READ: Register 0x01 -> 0x00
FAIL: Software reset (Register 0x01 <- 0x01, gelezen: 0x00)

this when is normal if i not had a fail on the soft reset then was somthing wrong.


WRITE: Register 0x16 <- 0x20
READ: Register 0x16 -> 0x00
FAIL: DOSR LSB (Register 0x16 <- 0x20, gelezen: 0x00)

WRITE: Register 0x17 <- 0x04
READ: Register 0x17 -> 0x00
FAIL: DAC clock enabled (Register 0x17 <- 0x04, gelezen: 0x00)

this to i have no explination whe the readback is not the same like the write..

only that the data cheat say not to write and only default value.

WRITE: Register 0x1F <- 0xC2
READ: Register 0x1F -> 0xC6
FAIL: Power up HPL/HPR (Register 0x1F <- 0xC2, gelezen: 0xC6)
this when is also normal because D2 bit you can not change.



best regard,
Matthias

Hi Matthias,

I think there is a mistake in the register addresses. The DOSR address is 0x0e, not 0x16 like your code.

The same is for the DAC clock enable, though I'm not sure exactly which clocking you are trying to turn on.

Best regards,
Jeff McPherson

hi jeff,


ik have checket indeed the name was wrong. de feedback name is the name ik give to the register.
i put the wrong text for this registers.


bud the problem is still the same. 

Best regards,

Matthias