Tool/software:
Currently, some of our products are experiencing a sound issue. The sound is robotic and occurs randomly. Restarting the device or gently touching the PCB can sometimes resolve the issue, but it can also make it worse.
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Tool/software:
Hi Bayram,
Issues like this often come from marginal timing failures on the I2S lines (BCLK/FSYNC) some small glitches on the clocks can cause strange errors and cause the device to get stuck in some incorrect state.
We have also seen these issue happen on some I2S masters if the clocks are changes on the fly. or it can be caused by marginal signal integrity issues. in your case by touching the device you are likely adding a small amount of shunt capacitance to the clocks which is affecting the signals. either causing ever
Can you please refer to section 5.9 in the datasheet and check for any possible timing violations? you may also try by adding a small (22,33 ohm) series resistor to the source of the I2S clocks (BCLK/FSYNC)
Regards,
Arthur
Hi Arthur,
AutoRate detection is active. When I monitor the 0x11 TDM Clock detection register in both states (normal operation and failure scenarios), the detected values are the same: FS_RATE is 16kHz and FS_RATIO is 32.
I tried disabling AutoRate and manually setting the FS_RATE to 16kHz, but I could not find the FS_RATIO register to configure. In this case, I could not play any sound.
Hi Bayram,
Can you investigate the I2S Clocks? are there any notable reflections or other notable issues?
Please refer to the section 5.9 in the datasheet for the timing requirements.
Do you have the provision to add some small series termination or shunt capacitance to the I2S Clocks?
Regards.
Arthur
Hi Arthur,
Here is the clock line. There is a bit of overshoot. Do you think this could be the reason for timing failures?
I will try to add series resistor and share the results.
Hi Bayram,
This does appear to be some type of reflection. this is BCLK? I assume due to the frequency.
Please do try adding something like 22 or 33 ohms in series and see if the result can be more stable.
Regards,
Arthur
Hi Arthur,
Thank you for your support.
Adding a series resistor to the BCLK has greatly improved the signal edges. I’m optimistic that the issue is resolved. Since it’s a random occurrence, I’ll need to conduct additional tests to confirm.
Hi Bayram,
I hope it is working! these types of issues are always a bit tricky to debug because they are not caught by our normal interrupt/fault reporting.
Regards,
Arthur