TLV320AIC3204: Performance Issues: Channel Discrepancy and Noise Floor Concerns

CODEC_REGWRITE(AIC3204_PAGE_CTRL, 0x00);

    // Initiate SW reset (PLL is powered off as part of reset)
    CODEC_REGWRITE(AIC3204_SW_RST, 0x01);

    // Program clock settings

    // Default is CODEC_CLKIN is from MCLK pin. Don't need to change this.
    // Power up NDAC and set to 1
    CODEC_REGWRITE(AIC3204_NDAC, 0x81);

    // Power up MDAC and set to 4
    CODEC_REGWRITE(AIC3204_MDAC, 0x84);

    // Power up NADC and set to 1
    CODEC_REGWRITE(AIC3204_NADC, 0x81);

    // Power up MADC and set to 4
     CODEC_REGWRITE(AIC3204_MADC, 0x84);

    // Program DOSR = 128
    CODEC_REGWRITE(AIC3204_DOSR, 0x80);

    // Program AOSR = 128
    CODEC_REGWRITE(AIC3204_AOSR, 0x80);

    // Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
    //   CODEC_REGWRITE(AIC3204_CODEC_IF, 0x20);
    CODEC_REGWRITE(AIC3204_CODEC_IF, 0x30);     // 32 bit mode
    // Program the DAC processing block to be used - PRB_P1
    CODEC_REGWRITE(AIC3204_DAC_SIG_PROC, 0x01);
    // Program the ADC processing block to be used - PRB_R1
    CODEC_REGWRITE(AIC3204_ADC_SIG_PROC, 0x01);
    // Select Page 1
    CODEC_REGWRITE(AIC3204_PAGE_CTRL, 0x01);
    // Enable the internal AVDD_LDO:
    CODEC_REGWRITE(AIC3204_LDO_CTRL, 0x09);
    //
    // Program Analog Blocks
    // ---------------------
    //
    // Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO
    CODEC_REGWRITE(AIC3204_PWR_CFG, 0x08);
    // Enable Master Analog Power Control
    CODEC_REGWRITE(AIC3204_LDO_CTRL, 0x01);
    // Set Common Mode voltages: Full Chip CM to 0.9V and Output Common Mode for Headphone to 1.65V and HP powered from LDOin @ 3.3V.
    CODEC_REGWRITE(AIC3204_CM_CTRL, 0x33);
    // Set PowerTune Modes
    // Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-AB driver.
    CODEC_REGWRITE(AIC3204_PLAY_CFG1, 0x00);
    CODEC_REGWRITE(AIC3204_PLAY_CFG2, 0x00);
    // Set ADC PowerTune mode PTM_R4.
    CODEC_REGWRITE(AIC3204_ADC_PTM, 0x00);
    // Set MicPGA startup delay to 3.1ms
    CODEC_REGWRITE(AIC3204_AN_IN_CHRG, 0x31);
    // Set the REF charging time to 40ms
    CODEC_REGWRITE(AIC3204_REF_STARTUP, 0x01);
    // HP soft stepping settings for optimal pop performance at power up
    // Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling
    // capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs �pop� sound.
    CODEC_REGWRITE(AIC3204_HP_START, 0x25);
    // Route Left DAC to HPL
    CODEC_REGWRITE(AIC3204_HPL_ROUTE, 0x08);
    // Route Right DAC to HPR
    CODEC_REGWRITE(AIC3204_HPR_ROUTE, 0x08);
    CODEC_REGWRITE(0x0e, 0x08);
    CODEC_REGWRITE(0x0f, 0x08);
    CODEC_REGWRITE(0x12, 0x3a);
    CODEC_REGWRITE(0x13, 0x3a); //Gain-0DB
        // We are using Line input with low gain for PGA so can use 40k input R but lets stick to 20k for now.
    // Route IN2_L to LEFT_P with 20K input impedance
    CODEC_REGWRITE(AIC3204_LPGA_P_ROUTE, 0x20);
    // Route IN2_R to LEFT_M with 20K input impedance
    CODEC_REGWRITE(AIC3204_LPGA_N_ROUTE, 0x20);
    // Route IN1_R to RIGHT_P with 20K input impedance
    CODEC_REGWRITE(AIC3204_RPGA_P_ROUTE, 0x80);
    // Route IN1_L to RIGHT_M with 20K input impedance
    CODEC_REGWRITE(AIC3204_RPGA_N_ROUTE, 0x20);
    // Unmute HPL and set gain to 0dB
    CODEC_REGWRITE(AIC3204_HPL_GAIN, 0x06);
    // Unmute HPR and set gain to 0dB
    CODEC_REGWRITE(AIC3204_HPR_GAIN, 0x06);
    // Unmute Left MICPGA, Set Gain to 0dB.
    CODEC_REGWRITE(AIC3204_LPGA_VOL, 0x00);
    // Unmute Right MICPGA, Set Gain to 0dB.
    CODEC_REGWRITE(AIC3204_RPGA_VOL, 0x00);
    // Power up HPL and HPR drivers
    CODEC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x30);


    CODEC_REGWRITE( AIC3204_PAGE_CTRL, 1); //page1
    CODEC_REGWRITE( 0x47, 0x32); //analog input quick charging configure
    CODEC_REGWRITE( 0x7b, 0x01); //power up config
    CODEC_REGWRITE( 0x33, 0x60); //---------0x78 used fail-------jian added ----MICBIAS
    CODEC_REGWRITE( 0x37, 0x80);
    CODEC_REGWRITE( 0x39, 0x10); // IN1L to RIGHT MICPGA with 10k ohm
    CODEC_REGWRITE( 0x3c, 0x2b); // 0x23 ==> 20dB Right MICPGA VOL --5a-45DB  5e--47db  :3d--ap实际测试25DB增益---跟客户样品一致 （一般30DB
    CODEC_REGWRITE( AIC3204_PAGE_CTRL, 0); // page0
    CODEC_REGWRITE( 0x54, 0x00); // _jian R_ADC volume 20DB
    CODEC_REGWRITE( 0x51, 0xc0);//
    CODEC_REGWRITE( 0x52, 0x00);//

    // Wait for 2.5 sec for soft stepping to take effect
    delay_milliseconds(2500);


    //
    // Power Up DAC/ADC
    // ----------------
    //
    // Select Page 0
    CODEC_REGWRITE(AIC3204_PAGE_CTRL, 0x00);
    // Power up the Left and Right DAC Channels. Route Left data to Left DAC and Right data to Right DAC.
    // DAC Vol control soft step 1 step per DAC word clock.
    CODEC_REGWRITE(AIC3204_DAC_CH_SET1, 0xd4);
    // Power up Left and Right ADC Channels, ADC vol ctrl soft step 1 step per ADC word clock.
    CODEC_REGWRITE(AIC3204_ADC_CH_SET, 0xc0);
    // Unmute Left and Right DAC digital volume control
    CODEC_REGWRITE(AIC3204_DAC_CH_SET2, 0x00);
    // Unmute Left and Right ADC Digital Volume Control.
    CODEC_REGWRITE(AIC3204_ADC_FGA_MUTE, 0x00);