TAS6754Q1EVM: Conditions under which Clock Error Event occur

Hi Shota

 On the EVM, there's no device could generate TDM clock. If no external clock source, you could only test with I2S clock settings.

 To test TDM, you need to externally provide SCLK/FSYNC/SDIN, through jumper J11/J14/J15.

Thank you for your reply.

I understood that EVM does not have a TDM generation device.

Currently, I am inputting the TDM signal to EVM from an external source.

(SCLK=12.288MHz, LRCLK=48kHz)

Before: the above configuration was outputting SPK normally.

Current: when I changed the TDM cable, a clock error occurred.

To solve Clock error, I would like to know the conditions under which Clock error occurs.

I could not find the detailed conditions from the datasheet.

Hi Shota

Shota Ueyama said:

To solve Clock error, I would like to know the conditions under which Clock error occurs.

Possible conditions would be:

1. When SCLK or LRCLK is missing, or incorrect frequency.

2. When SLCK/LRCLK ratio is not correct.

Sorry for the delay of replying.

If it is possible, could you tell me the actual values?

1. When SCLK or LRCLK is missing, or incorrect frequency.
-> Ex. Frequency offset by +/- 5%.

2. When SLCK/LRCLK ratio is not correct.
-> Ex. SLCK/LRCLK ratio offset by +/- 5.