TLV320AIC3110: TLV320AIC3110

Tappeta Lakshmi Sai Geetha

Part Number: TLV320AIC3110

Tool/software:

Hi,

Can you please provide a code to configure the codec in playback and record mode.
The EVM code is not working for me. Without using the evm on my fpga i am configuring the codec with i2s. And try to play a sine wave on pc and connect it to codec on fpga an configure the codec in record mode and configuring the i2s in receive mode to receive the samples from codec on receive buffer of i2s. But I am not receiving the correct data not getting sine wave samples.

Thanks and Regards,
T. Lakshmi Sai Geetha.

6 months ago

0 Jeff McPherson 6 months ago

TI__Mastermind 46645 points

Hi Geetha,

The EVM script will work for 90% of applications. The things to adjust are 1) the input pin configurations (i.e. which pin will the pc sine wave be coming in to) and 2) adjust the clocking set up per the I2S clock frequencies being used. This spreadsheet helps you confirm that your clocking is valid and gives the expected values: https://www.ti.com/tool/download/SLAR163

Once those two things are adjusted for your set up the script should work as a whole.

Best regards,
Jeff McPherson

0 Tappeta Lakshmi Sai Geetha 6 months ago in reply to Jeff McPherson

Prodigy 30 points

Hi Jeff,

Yes I understand but even when I configure it in controller mode I am not getting the BCLK clocks so that mu data is not going on to the bus from I2S side.

Thanks and Regards,
T. Lakshmi Sai Geetha.

0 Jeff McPherson 6 months ago in reply to Tappeta Lakshmi Sai Geetha

TI__Mastermind 46645 points

Hi Geetha,

So you are missing the BCLK output? Can you share your clock frequencies? What is the MCLK given to the device and what is the desired BCLK and WCLK?

Have you enabled controller mode by turning BCLK and WCLK into an output?

Thanks,
Jeff McPherson

0 Tappeta Lakshmi Sai Geetha 6 months ago in reply to Jeff McPherson

Prodigy 30 points

Hi Sir,

APB clock that we are giving is 8MHZ and when I configure I2S in controller mode I am getting BCLK and WCLK with clock frequency 1.6 MHZ once I load the bit stream. When configuring the codec as controller mode after loading the bit stream before configuration only getting the BCLK clock.
And I am enabling the BCLK and WCLK into an output.

Even when I am configuring it as target mode in playback mode and recording mode it is not working with the EVM script.

Thanks and Regards,
T.Lakshmi Sai Geetha.

0 Jeff McPherson 6 months ago in reply to Tappeta Lakshmi Sai Geetha

TI__Mastermind 46645 points

Hi Geetha,

Target mode will not work if the FPGA does not give clocks to the device. No clocks are output from the device in target mode.

1.6MHz is very very high for WCLK and WCLK cannot be the same as BCLK. What are the desired values? Have you compared your clock configuration with this spreadsheet tool to make sure it is valid? https://www.ti.com/tool/download/SLAR163

Best regards,
Jeff McPherson

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TLV320AIC3110: TLV320AIC3110