TAC5112: BCLK and FSYNC outputs

Ryu Yamashita

Part Number: TAC5112

Tool/software:

Hi team,

I am using it in controller mode and have CLK input to GPI1, but the BCLK and FSYNC pins are not outputting their respective CLKs.
Is there some register setting I need to do?
The registers I am setting are as follows

Page	Register Address	Register Name	Setting Register
0	0x0D	GPI_CFG	0x02
0	0x0F	INTF_CFG0	0x60
0	0x1A	PASI_CFG0	0x60
0	0x1B	PASI_TX_CFG0	0x06
0	0x26	PASI_RX_CFG0	0x60
0	0x37	CNT_CLK_CFG2	0x31

Best Regards,
Ryu

5 months ago

0 Mir Jeffres 5 months ago

TI__Genius 12695 points

Hi Ryu,

Sorry about the delay, I will test this out tomorrow. Are these the only registers you are setting?

Best,
Mir

0 Ryu Yamashita 5 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

That is correct.

Best Regards,
Ryu

0 Mir Jeffres 5 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu,

What are the clocks you want to generate? These registers are just to configure CCLK input and set it to 12.288MHz. I also notice that you have set the output sample rate as a multiple of 44.1, which is not an integer multiple of 12.288MHz. This is fine, we can configure the PLL, but let's figure out what clocks you are actually wanting to output before I calculate all this for you. I can suggest some more registers to set, but as of now, you have not configured the desired sample rate out (done with register 0x32 on page 0). Let me know the desired sample rate and I can help more here.

Best,
Mir

0 Ryu Yamashita 5 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

I am using 22.5792 MHz for CCLK, 44.1 kHz for FSYNC, and 64*FS for BCLK.

Best Regards,
Ryu

0 Mir Jeffres 5 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu,

Here is the code I used to set the clock dividers, this gives FSYNC of 44.1k and 2.8224MHz as the BCLK, for a input CCLK of 22.5792 MHz. I will attach configuration code to this as well tomorrow - sorry, didn't have time to generate that part. I was using PPC3 to configure the device originally, if you paste this into the i2c command window in controller mode, it may work.

w a0 00 03 
w a0 32 80 #pll_pdiv_inclk is cclk
w a0 36 00 #no div by 2
w a0 35 02 #pdiv=2
w a0 38 08 #j=8
w a0 37 00 #d=0
w a0 39 20 #ndiv=1, pdmdiv=1
w a0 3a 41 #mdiv=16, dig adc modclk div=2
w a0 35 02 #pll pdiv =2
w a0 33 00 #sasi bclk source pll out
w a0 34 90 #dig nm input is cclk, nm div input is pll output 
w a0 3b 10 #dac modclk 2x disabled, dig dac modclk div=1
w a0 3c 20 #pasi bclk div =32
w a0 3d 01 #sasi bclk div=1
w a0 3e 02 #ana nm div=2
w a0 3f 00

w a0 44 07 #enable ndiv, mdiv, pdm div
w a0 45 ff #enable all other dividers

Best,
Mir

0 Ryu Yamashita 5 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Thanks for the code.
Can I have the code including the configuration?

Best Regards,
Ryu

+1 Mir Jeffres 5 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu,

The full setup code depends on if you want DAC or ADC functionality, or both. The script here is based off of the example in the datasheet for both being on. I was able to get the clocks outputting correctly and a differential output on OUT1 with this configuration. Let me know if you have questions about the config or any issues.

# Page 0 Register Writes
w a0 00 00
w a0 01 01 #SW Reset
d 01
# Page 0 Register Writes
w a0 00 00
w a0 02 09 #Exit Sleep Mode with DREG and VREF Enabled
w a0 1a 70 #I2S protocol with 32-bit word length
w a0 1b 06 #internal fsync and bclk used for asi data generation
w a0 0d 02 #GPI1 is GPI
w a0 0f 60 #CCLK is GPI1
w a0 26 60 #internal fsync and bclk used for controller mode input data latching

w a0 32 51 #bin 20d (48k, includes 44.1k), 1% tolerance, manual clock config
w a0 34 08 #PLL enabled, fixed cclk frequency as input clock
w a0 35 02 #MSB for FSYNC to CCLK ratio=512
w a0 36 00 #ratio=512
w a0 37 f1 #24.576MHz CCLK, pasi in controller mode, sr is a multiple of 44.1khz
w a0 38 80 #use internal BCLK for FSYNC generation 
w a0 39 40 #MSB for BCLK to FSYNC ratio = 64

w a0 4d 00 #VREF set to 2.75V for 2Vrms differential fullscale input
w a0 50 00 #ADC Channel 1 configured for AC-coupled differential input with 5kOhm input impedance and audio bandwidth
w a0 55 00 #ADC Channel 2 configured for AC-coupled differential input with 5kOhm input impedance and audio bandwidth
w a0 64 20 #DAC Channel 1 configured for differential output with 0.6*Vref as common mode
w a0 65 20 #DAC OUT1P configured for line out driver and audio bandwidth
w a0 66 20 #DAC OUT1M configured for line out driver and audio bandwidth
w a0 6b 20 #DAC Channel 2 configured for differential output with 0.6*Vref as common mode
w a0 6c 20 #DAC OUT2P configured for line out driver and audio bandwidth
w a0 6d 20 #DAC OUT2M configured for line out driver and audio bandwidth


w a0 00 03 #page 3
w a0 32 80 #pll_pdiv_inclk is cclk
w a0 36 00 #no div by 2
w a0 35 02 #pdiv=2
w a0 38 08 #j=8
w a0 37 00 #d=0
w a0 39 20 #ndiv=1, pdmdiv=1
w a0 3a 41 #mdiv=16, dig adc modclk div=2
w a0 35 02 #pll pdiv =2
w a0 33 00 #sasi bclk source pll out
w a0 34 90 #dig nm input is cclk, nm div input is pll output 
w a0 3b 10 #dac modclk 2x disabled, dig dac modclk div=1
w a0 3c 20 #pasi bclk div =32
w a0 3d 01 #sasi bclk div=1
w a0 3e 02 #ana nm div=2
w a0 3f 00

w a0 44 07 #enable ndiv, mdiv, pdm div
w a0 45 ff #enable all other dividers


w a0 00 00 #page 0
w a0 76 cc #Input Channels 1, 2 enabled; Output Channels 1, 2 enabled
w a0 78 c0 #ADC, DAC Powered Up

Best,
Mir

0 Ryu Yamashita 5 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Thanks for sharing the Register with me.
It worked successfully.
I just have a few things I would like to know.
w a0 38 80 #use internal BCLK for FSYNC generation is grayed out in PPC3 and cannot be set.
Do you know what the cause is?
Also, is there any way to save the register in PPC3?
When I save and load a project, the registers are cleared and I have to re-set them each time.

Best Regards,
Ryu

0 Mir Jeffres 5 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi,

Does your greyed out internal BCLK setting look like this?

This is a controller mode setting, which is greyed out when the device is in target mode. When you switch to controller mode that block becomes active and editable.

I believe if you run the script in the I2C monitor and then save the configuration with CTRL+S or the top left corner dropdown->Save, you can then load it again on startup. However, there is a chance for bugs there, PPC is always being updated and has had issues with saving all settings in the past. Ideally in your end application you would run the script on startup, PPC is usually used as a tool to generate these configuration scripts. So, you can definitely try to save the config as I described, but if there are any issues that you notice, you may need to run it again anyway.

Best,
Mir

0 Ryu Yamashita 5 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Thank you for your response.
Please tell me a little more.

w a0 35 02 #MSB for FSYNC to CCLK ratio=512
I was not sure what this means and why it is 512.

Also,you don't have any information about Clocktree yet, right?
I would like to know how NDIV and others are connected.
Also, the SDA pin is listed as a digital input, is this a mistake in the I/O description?

Best Regards,
Ryu

+1 Mir Jeffres 5 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi,

The register 0x35 contains setting the most significant bits (MSB) for the CCLK to FSYNC ratio - remember CCLK is the same thing as MCLK for I2S. Register 0x36 has the LSB. Since MCLK/FSYNC = 22.5792MHz/44.1kHz = 512, we need to set this ratio to 512, and 512 in binary is 0x200 so we set register 0x36 to 00 and 0x35 to 02.

I am the clock tree point of contact for this device, am writing the manual PLL app note now. But, you can configure the tree with PPC3, if you click "Configure PLL" in the Audio Serial Bus tab you will see the tree, although it is broken up in a way that is confusing. If you are in controller mode, there will be a controller tab at the top, this is where NDIV is set. I prefer to just set PASI_BDIV instead of NDIV to generate the BCLK from the output of the PLL. Remember to enable the dividers, this can be done with I2C since there are not always enable check boxes in this GUI. The script I provided does this and I checked to make sure it works as expected.

Also, I think SDA is generally bidirectional, so it would be I/O and not just input, you are correct. It is a normal I2C data line, nothing unique about this device's I2C connection.

Let me know if you have more questions.

Best,
Mir

0 Ryu Yamashita 5 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Thanks for the reply.
I understand now.
I am waiting for the release of the application note.

Please tell me again about the grayout.
The register is also in controller mode, but is grayed out as shown below.
The EVA board seems to only produce sound on Lch L because of this.
By the way, even if I set 0x37 (CNT_CLK_CFG2) to 0xf1 (24.576MHz CCLK, pasi in controller mode, sr is a multiple of 44.1khz) and press the Read All Register button on PPC3, MSB of 0x38 remains grayed out.
Do you know what the cause is?

Best Regards,
Ryu

+1 Mir Jeffres 5 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu,

Is this screenshot after running my script? My PPC has that bit greyed out but it is set to 1, from the line "w a0 38 80" setting it. I'm not sure why it is greyed out in the register configuration, it may be a bug with PPC... let me know if the register changes after you run my script.

The L channel only making sound is likely not due to a controller mode, but may be because of I2S/TDM differences, are you using I2S or TDM mode? You may need to change channel 2 to RIGHT slot 0 instead of left slot 1. This is in the Audio Serial Bus tab, I screenshotted what you might need to change here:

In the script, you can add the line "w a0 29 30" to page 0 to configure this. However, it should be set automatically when you run the script with I2S mode.

If you are getting any audio out, then the FSYNC generation was successful, otherwise there is no way for the I2S data to transmit. So, hopefully this is an ASI configuration issue and not related to generating the clocks.

Best,
Mir

0 Ryu Yamashita 5 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Adding “w a0 29 30” worked as intended.
Thank you very much.

Best Regards,
Ryu

+1 Mir Jeffres 5 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi,

Glad it worked. Also, I found out that the internal/external BCLK and FSYNC problem in registers 0x38 and 0x3a was a known bug and has been fixed in the most recent iteration of PPC3, it should be pushed to a public release in the next few months. Again this is a GUI-only issue, so any register settings done manually with I2C should fix issues that you have with the GUI. Let me know if you have more questions.

Best,
Mir

0 Ryu Yamashita 4 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

I'm sorry, could you please add to that?
It seems that there is no output on DOUT of ADC.
The waveform looks exactly like this.
I have confirmed that the input analog signal is coming in correctly.
Are there additional registers that should be set?

Best Regards,
Ryu

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi,

Can you provide your script that you are having issues with getting the DOUT? If no script, can you provide register dump? What is your screenshot of? Can you measure your clocks coming out of the device to make sure they are as you expect?

Best,
Mir

0 Ryu Yamashita 4 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

The register is as originally set up that you gave me.
The w a0 29 30 has been added.
Clock is as expected.

Best Regards,
Ryu

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Just to make sure, did we resolve the problem? Or do you have more questions?

-Mir

0 Ryu Yamashita 4 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

The problem has not been solved.
DOUT is not outputting as expected.

There are a few more points of concerns.
w a0 3b 10 #dac modclk 2x disabled, dig dac modclk div=1
I think this is a mistake for 08, not 10.
The comment after that says sasi bclk div=1.
Also, in the clock tree on the GUI, I see SASI_BCLK in PASI, is this a correct?

When are you planning to release the application notes for the clock tree?
I feel it is necessary to create the software.

Best Regards,
Ryu

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu-san,

Sorry about that, yes that should be 0x08 instead of 0x10 for the comment I wrote. SASI_BCLK is separate than PASI_BCLK, if you are using the secondary ASI for your processing then you would set SASI_BCLK instead of PASI_BCLK. The divider I was referencing in that comment is to generate the BCLK in controller mode, and it divides down from CLK_SYS or the output of NDIV, as shown in this page of the GUI.

Are you not getting any clock outputs? What happens when you run the last script I sent? I had it working on an EVM as I described so I am not sure what your issue is. Can you measure the BCLK and WCLK out, as well as the MCLK/CCLK in? How are you receiving the audio data from the board, how to measure it?

Best,
Mir

0 Ryu Yamashita 4 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Thanks for the reply.
I understood that 0x08 is correct.
I was also concerned about the following part
SASI_BCLK is being input to PASI_BDIV.
I was wondering if this is a problem.

It is not that CLK is not coming out.
The analog signal input to IN1P (IN1M) is not coming out of DOUT.
Is there anything additional I should set up?

Ryu Yamashita said:
When are you planning to release the application notes for the clock tree?
I feel it is necessary to create the software.

Also, how about this?
Can you give me an approximate date?

Best Regards,
Ryu

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi, give me a day to respond here, sorry about the delay.

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu-san,

I raised a ticket with our PPC team to fix that bug in the GUI. I checked to make sure and the divider marked PASI_BDIV in the middle of your screenshot changes the PASI_BDIV register (0x3c in page 3), the connecting lines are wrong.

For no DOUT, were you running my script I sent? Make sure you ran the lines at the end, these enable/"turn on" the device:

w a0 00 00 #page 0
w a0 76 cc #Input Channels 1, 2 enabled; Output Channels 1, 2 enabled
w a0 78 c0 #ADC, DAC Powered Up

How are you configuring the device, and if you are still having problems after this recommendation can you send me a register dump? You can get it from PPC3 here, choose dump to file and then attach the file to our thread here:

Best,
Mir

0 Ryu Yamashita 4 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Mir Jeffres said:
I raised a ticket with our PPC team to fix that bug in the GUI. I checked to make sure and the divider marked PASI_BDIV in the middle of your screenshot changes the PASI_BDIV register (0x3c in page 3), the connecting lines are wrong

Sorry.
I wasn't clear.
Are you saying that PASI is a misnomer for SASI?

I was able to work on ADC.
Thank you very much.
I have some concerns.
I set the following registers and it worked.
w a0 00 03 #page 3
w a0 3b 10 #dac modclk 2x enabled, dig dac modclk div=2
w a0 3f 0c #

What register is w a0 3f?
Also, when I set w a0 3b back to 08, the sound was distorted.
Is there any possible cause?

Best Regards,
Ryu

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi,

PASI stands for Primary ASI and SASI is Secondary ASI. They are not the same thing. I was just saying that the lines that you highlighted are drawn wrong in the GUI - trust the number box labels at the bottom of that screen and NOT the drawn lines. The GUI will be updated to fix this issue in the next release.

Register 0x3F sets the DEM divider, and 0x3B has some DEM divider value capability as well. 0x3B has the "high performance mode" capability, that should always be on for this sample rate (it sets the MODCLK rate to be high), and DEM always needs to be a factor of 2 higher than the MOD clock, this is why MODCLK DIV is 2. Keep all the defaults on the reserved registers to keep DEM dividers = 1.

Make sure you set these registers:

w a0 00 03
w a0 3b 10
w a0 3f 00

Best,
Mir

0 Ryu Yamashita 4 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Thanks for the reply.
I will send you the register file with the correct output.
I still had to use “w a0 3f 00” to get the output.
If I don't do “0c”, it doesn't output.
Is there something wrong?

Best Regards,
Ryu

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu,

I will need another day to look over this, sorry about the delay. We will figure this out soon. I have a feeling that we can get your config to work in automatic mode, and then we do not even need to configure these dividers. You are still using CCLK = 22.5792MHz right?

Best,
Mir

0 Ryu Yamashita 4 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

Mir Jeffres said:
You are still using CCLK = 22.5792MHz right?

This is correct.
I am waiting for your reply.

Best Regards,
Ryu

0 Mir Jeffres 4 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

I need one more day - I almost have it working in auto mode, but having a few issues with my config.

+1 Mir Jeffres 3 months ago in reply to Mir Jeffres

TI__Genius 12695 points

Hi Ryu,

I have a new script for you - it should work for both ADC and DAC with auto clock configuration so there are no issues with these registers I had set before. Please try it and see if it works for your system. This is using CCLK=22.5792MHz on GPI1, and it outputs WCLK = 44.1kHz and BCLK=2.8224MHz. So sorry about the delay on this.

w a0 00 00 # Set page 0
w a0 01 01 # Software Reset
w a0 02 09 # Wake up with AVDD > 2v and all VDDIO level
w a0 0d 02 # GPI1 is GPI
w a0 0f 60 # CCLK is GPI1
w a0 10 50 # Configure DOUT as Primary ASI (PASI) DOUT
w a0 19 00 # 1 data input and 1 data output for PASI
w a0 1a 70 # PASI I2S, 32 bit format
w a0 1e 20 # PASI Ch1 on Left slot 0
w a0 1f 30 # PASI Ch2 on Right slot 0
w a0 32 50 # PASI Fs=48KHz with auto clock configuration
w a0 34 48 # PLL always enabled with fractional allowed and from fixed clk frequency
#wclk to fsync ratio = 512
w a0 35 02 #MSB=10
w a0 36 00 #LSB=00 (for 512)

w a0 37 f0 #24.576MHz MCLK, multiple of 48k (this is auto shifted to outputting 44.1k when MCLK is supplied as 22.5792MHz)


w a0 38 80 # Use internal BCLK for FSYNC generation in controller mode
w a0 39 40 # Set controller mode BCLK/FSYNC ratio to 64 = h40

w a0 4d 00 #VREF set to 2.75V for 2Vrms differential fullscale input

w a0 50 00 # ADC Ch1 diff input, 5KOhm, 2Vrms ac-coupled, audio band
w a0 55 00 # ADC Ch2 diff input, 5KOhm, 2Vrms ac-coupled, audio band

w a0 64 20 #DAC Channel 1 configured for differential output with 0.6*Vref as common mode
w a0 65 20 #DAC OUT1P configured for line out driver and audio bandwidth
w a0 66 20 #DAC OUT1M configured for line out driver and audio bandwidth
w a0 6b 20 #DAC Channel 2 configured for differential output with 0.6*Vref as common mode
w a0 6c 20 #DAC OUT2P configured for line out driver and audio bandwidth
w a0 6d 20 #DAC OUT2M configured for line out driver and audio bandwidth

w a0 76 cc #Input Channels 1, 2 enabled; Output Channels 1, 2 enabled
w a0 78 c0 #ADC, DAC Powered Up

Best,
Mir

0 Ryu Yamashita 3 months ago in reply to Mir Jeffres

Genius 3685 points

Hi Mir,

It worked as expected with the register map you provided.
Thank you very much.
Also, when can we expect the application note for the clock tree?

Best Regards,
Ryu

0 Mir Jeffres 3 months ago in reply to Ryu Yamashita

TI__Genius 12695 points

Hi Ryu-san,

So glad it worked for you. App note should be out in the next few months. So sorry about the delays. I am happy to answer questions about clock tree and clock settings if you have more.

-Mir

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TAC5112: BCLK and FSYNC outputs