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TAC5242: Clocking Question

Frankie Conway
Prodigy 10 points
Part Number: TAC5242

Tool/software:

Hello,

I am looking to operate the TAC5242 in Target mode using an I2S interface with 32b word length and a sample rate of 192k.  To satisfy the requirements of the I2S interface that means I must use > 64 BCLK to FSYNC ratio since the first BCLK is not used.  This means I must generate a BCLK of 18.432MHz per table 7-5 (shown below).  What are the consequences of not being able to make the 18.432 clock perfectly?  If I am off by 100ppm is that an issue?  Is it ok if the BCLK to FSYNC ratio is still 96 even though the absolute FSYNC and BCLK frequencies are off?

Thank you for your help in advanced.

  • +1
    TI__Genius 12775 points

    Hi,

    It looks like you would need a clock of at least 12.288MHz, not 18.432MHz (I think you were off by a line in the table). 64 * 192k = 12.288MHz. These clocks have ~5% tolerance, but it would be for both WCLK and BCLK, they would still need to be synced, but if they are both off by up to 5%, the device should still work as expected.

    Let me know if you have more questions.

    Best,
    Mir 

  • 0 in reply to Mir Jeffres
    Prodigy 10 points

    Hello Mir, thanks for the reply.  That clock tolerance is good to know and also the fact that if both clocks are sync'd but off then it should still work fine.  One thing that might be unclear is how a Target mode I2S 32b word length interface works.  From this section in the datasheet, I was under the impression that I needed more than 32 BCLKs per slot:

    Since the MSB is latched in on the second clock, you must have more than 32 BCLK if you are going to use all 32 bits of representation.  Then when I was looking at the ratios it seemed that I couldn't just have a BCLK ratio of 66, so the first one that satisfied both the diagram and the verbiage below the diagram was a ratio of 96, which has 48 BLCKs per slot.  Is this a correct reading of the datasheet?

  • 0 in reply to Frankie Conway
    TI__Genius 12775 points

    Hi Frankie,

    For the I2S protocol, there is a 1 bit shift between data in/out and FSYNC, so 32 BCLK per channel is correct - you would want a ratio of 64 for 32 bit I2S clocks. Let me know if you have more questions about this!

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 10 points

    If there's only 32 BCLKs per channel, does that mean for a word length of 32 that the LSB for a given channel is latched in the first clock after a FSYNC transition?

  • +1 in reply to Frankie Conway
    TI__Genius 12775 points

    Hi,

    Yes, the LSB is latched 1 clock cycle after the FSYNC transition. You can see it in the screenshot you posted, the Left (Ch1) and Right (Ch2) bits are shown aligned with BCLK and FSYNC as they would be running in the device.

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 10 points

    Alright, that makes sense.  That was definitely a missing piece in my understanding.  My assumption was that a channel had to be done in a single FSYNC half-period.  Just to round out my understanding, there is no issue using an FSYNC to BCLK ratio of 96 with a 32b word with, it just runs the BCLK faster with throwaway clocks after the LSB of the data.  It would end up being a higher power solution than running with a ratio of 64.

    Thank you so much for taking the time to walk me through this.

  • +1 in reply to Frankie Conway
    TI__Genius 12775 points

    You can for this device since the internal automatic clock dividers support a ratio of 96 shown in table Table 7-7 of the datasheet. However, this may not be possible on ALL codecs, so keep this in mind. A higher ratio will lead to empty bit clock cycles after the 32 bits of data per FSYNC half-period. 

    -Mir

  • 0 in reply to Mir Jeffres
    Prodigy 10 points

    Got it, thanks again for the clarification.  All of this makes sense now.  Really appreciate it.