PCM3168A: DAC Output

Hi Arvind,

Do you expect to have a sine out? If so, you would need to decrease the gain out of the chip. What do you expect out, and can you supply your i2c commands you have set to achieve this configuration?

Best,
Mir

Hi Mir,

Thanks for your reply.

Yes, we are applying sine wave at input and expecting same sine wave at codec output, we tried to reduce gain, but we are getting same w/f and noise at output

Can you confirm if above circuit is ok?

We are using SPI for configuration (Gokul Lakshminarayanan   is discussing with you on same topic   PCM3168A: Interfaced PCM3168A(Slave) with ADSPBF527(Master) using SPI Communication - Issue in reading the MISO line)

0x40 0xC1 RESET CONTROL # should be fine, setting to single rate mode
0x41 0X07 DAC CONTROL 1 #slave mode, 24 bit left justified tdm mode
0x42 0x20 DAC CONTROL 2 #dac 3/4 disable? all other dac channels normal operation
0x43 0x00 DAC OUTPUT PHASE #normal output phase for all channels
0x44 0x00 DAC SOFT MUTE #disabled mute for all channels
0x45 0xCC DAC ZERO FLAG #dac8, dac7, dac 2, and dac 1 zero flag? this is read only...
0x46 0x80 DAC CONTROL 3 
0x47 200 DAC ATTENUATION #this reg could control all channels, but previous register ATMDDA does not allow it
0x48 200 DAC ATTENUATION #ch1 muted
0x49 200 DAC ATTENUATION #ch2 muted
0x4A 200 DAC ATTENUATION #ch3 muted
0x4B 200 DAC ATTENUATION #ch4 muted
0x4C 200 DAC ATTENUATION #ch5 muted
0x4D 0x00 DAC ATTENUATION #no attenuation for ff -> ch6 unmuted
0x4E 0x00 DAC ATTENUATION 
0x4F 0x00 DAC ATTENUATION 
0x50 0x01 ADC SAMPLING MODE #adc in single rate mode
0x51 0x07 ADC CONTROL 1 #24 bit left justified mode tdm format adc
0x52 0x00 ADC CONTROL 2 #normal operation
0x53 0x00 ADC INPUT CONFIGURATION #differential input for all channels
0x54 0x00 ADC INPUT PHASE #no phase changes
0x55 0x00 ADC SOFT MUTE #mute disabled
0x56 0x00 ADC OVERFLOW FLAG #overflow not detected
0x57 0x80 ADC CONTROL 3 #all channels w preset + master control so atad0 controls the attenuation
0x58 0xD7 ADC ATTENUATION #no attenuation on all channels of adc
0x59 0xD7 ADC ATTENUATION
0x5A 0xD7 ADC ATTENUATION
0x5B 0xD7 ADC ATTENUATION
0x5C 0xD7 ADC ATTENUATION
0x5D 0xD7 ADC ATTENUATION
0x5E 0xD7 ADC ATTENUATION

.

Regards,

Arvind Khalate

Hi Arvind,

Where are you adjusting the gain? I see that you copied my comments, but I do not see any change, and from 0x47-0x4f for DAC attenuation what does 200 mean? There is where you would be able to adjust the output volume/gain. Set the output register for the channel you desire to some attenuation until the clipping is no longer present.

What is the dBFS of the input signal you are providing to the DAC?

Best,
Mir

Hi,

I was just testing a different signal on this device and had this same thing happen when the clock was misaligned - make sure you are inverting frame clock when generating the clocks for your TDM mode.

Noninverted frame clock at -60dBFS input:

Inverted:

Let me know if you are able to fix your issue with this. If not can you take a scope capture of your I2S clocks so we can take a look and figure out how to adjust them?

Best,
Mir

Hi Mir,

Thank you.

I will try suggested configuration.

I have some waveform captured earlier, please see below w/f

Yellow - Frame sync(LRCKAD/DA)

Blue- SCKI and BCKLAD/DA

Data In and Data out

Regards,

Arvind