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TLV320ADC5120: TLV320ADC5120 – Unexpected Amplitude Output for 200mVpp 1 Hz Sine Wave Input

AJITH KUMAR
Intellectual 510 points
Part Number: TLV320ADC5120

Tool/software:

Hello TI Support Team,

We are currently working on TLV320ADC5120 IC. As part of our testing, we applied a 1 Hz sine wave signal with 200 mVpp to the ADC input. The ADC output waveform correctly shows a sinusoidal shape, indicating that the sampling and processing path is functional.

However, we observed that the amplitude of the output data does not correspond to the expected level based on the 200 mVpp input. Attached a screenshots of the waveform plots and the corresponding data in Excel, where you can clearly see the sinusoidal shape but with an amplitude that appears significantly lower than expected.

But when we have applied a 1 KHz with different voltage peak to peak, we have gotten a correct amplitude levels. which is shown in below screenshots,

Following is the register which we configure through i2c,

TLV320_WriteRegister(0x01, 0x01);

HAL_Delay(10);

TLV320_WriteRegister(0x02, 0x81);

HAL_Delay(10);

TLV320_WriteRegister(0x41, 0x40);

HAL_Delay(10);

TLV320_WriteRegister(0x3B, 0x70);

HAL_Delay(10);

TLV320_WriteRegister(0x22, 0x41);

HAL_Delay(10);

TLV320_WriteRegister(0x2B, 0x45);

HAL_Delay(10);

TLV320_WriteRegister(0x73, 0xF0);

HAL_Delay(10);

TLV320_WriteRegister(0x74, 0xF0);

HAL_Delay(10);

TLV320_WriteRegister(0x75, 0x60);

HAL_Delay(10);

  • Is there anyother register, we need to configure. 

  • What could cause this discrepancy in amplitude despite the correct waveform shape in lower frequency?

  • Are there any specific gain, scaling, or PGA settings we should double-check?

  • Could any filtering or digital processing within the TLV320ADC5120 be influencing the observed output amplitude?

We look forward to your guidance. Thanks in advance.

Best regards,
Ajith Kumar

  • 0
    TI__Expert 7720 points

    Hi Ajith,

    The TLV320ADC5120 has an internal digital high-pass filter. the setting for this filter is described in the DSP_CFG0 register (Page 0 Register 0x6B):

    Assuming that the sampling rate is 48kHz, by default the cut-off frequency of this high-pass filter is 12Hz, which may explain why the amplitude is lower for a 1Hz signal, but as expected for 1kHz signal.

    You can set the HPF_SEL field in this register to 0 to make this an all-pass filter and check the 1Hz frequency measurement again.

    Thanks and Regards,

    Lakshmi Narasimhan

  • 0 in reply to Lakshmi Narasimhan Badrinarayanan
    Intellectual 510 points

    Hi Lakshmi Narasimhan,

    Thanks for your response,

    We found an issue with IC After repeated tests, the ADC stopped responding over I²S.

    No variation in I²S digital output regardless of input signal. No sign of corrupted data, just zeros. Device is now non-functional and likely damaged. 

    We replaced the IC, and for a couple of runs it worked fine, but now we consistently receive zero values only from the ADC output (via I2S), despite correct input. The replaced IC also damaged.

    • Input is 1 kHz, 200 mVpp sine wave (confirmed by oscilloscope).

    • I2S and I2C interfaces are properly initialized.

    • After power-on and init, all output samples are 0.

    • We suspect some internal register misconfiguration or initialization sequence issue, especially after IC replacement.

    Below is our initialization code for the TLV320ADC5120:

    void TLV320_Init(void)
    {
    TLV320_WriteRegister(0x02, 0x81); // Power-up
    HAL_Delay(10);

    TLV320_WriteRegister(0x41, 0x40); // MICBIAS setup
    HAL_Delay(10);

    TLV320_WriteRegister(0x3B, 0x70); // Analog config
    HAL_Delay(10);

    TLV320_WriteRegister(0x22, 0x41); // Clock settings
    HAL_Delay(10);

    TLV320_WriteRegister(0x2B, 0x45); // Clock settings
    HAL_Delay(10);

    TLV320_WriteRegister(0x73, 0xF0); // Audio format config
    HAL_Delay(10);

    TLV320_WriteRegister(0x74, 0xF0); // Audio format config
    HAL_Delay(10);

    TLV320_WriteRegister(0x75, 0x60); // Audio format config
    HAL_Delay(10);
    }

    Could missing any of the above critical registers (e.g., routing or gain registers) lead to a 0 output from ADC?


    Any feedback or recommendations would be very helpful.

    Thanks and Regards,
    A Ajith Kumar

  • 0 in reply to AJITH KUMAR
    TI__Expert 7720 points

    Hi Ajith,

    While the device is active and recording is happening, can we read back the device's status registers?
    Registers 0x15, 0x76 and 0x77?

    Thanks and Regards,

    Lakshmi Narasimhan

  • 0 in reply to Lakshmi Narasimhan Badrinarayanan
    Intellectual 510 points

    Hi Lakshmi Narasimhan,

    In these status registers ,

    0x15 - > 0xFF ; Invalid sample rate, Invalid ratio 

    0x76 -> 0x00 ; ADC or PDM channel 1 power status. 0d = ADC or PDM channel is powered down. 

    ADC or PDM channel 2 power status. 0d = ADC or PDM channel is powered down.

    0x77 - > 0xC0; 
    6d = Device is in active mode with all ADC or PDM channels turned off.



    We look forward to your guidance.

    Thanks and Regards,

    A. Ajith Kumar

  • 0 in reply to AJITH KUMAR
    TI__Expert 7720 points

    Hi Ajith,

    It looks like the valid BCLK, FSYNC may not be reaching the device. That can explain the ASI_STS register that you are seeing.

    1) Can you confirm that the BCLK/FSYNC signals are seen at the device pins/

    2) Can you confirm that the I/O level of the BCLK/FSYNC signals provided to the device matches the IOVDD voltage?

    Thanks and Regards,

    Lakshmi Narasimhan