TPA6304-Q1: About Fault function

Jingkun Wang

Intellectual 295 points

Part Number: TPA6304-Q1

Tool/software:

Hello TI team,

Now, we have a special application that uses only 1CH of this IC.

Only using channel 3 for subwoofer, and other channels are open.

At this application, the DC Load Diagnostics can't pass at MUTE to Play.

This fault signal is always high-low output.

So now we modified the configuration process:

DC Diag
↓
Re-configurate 0x1E: 0x59 → 0x18

Using this configuration, in the play mode

If overcurrent occurs in playback mode (short to battery/short to GND)
↓
Fault pin outputs low
↓
Writing bit7 of 0x30 to clear fault
↓
Fault pin still keeps low even if the fault events released

How can we set it so that the Fault pin status can reflect the fault information in real time?

Or how do you recommend setting up fault detection in this application scenario?

Best Regards!

Wang Jingkun

4 months ago

0 Shadow He 4 months ago

TI__Mastermind 49430 points

Hi Jingkun

Jingkun Wang said:
Writing bit7 of 0x30 to clear fault
↓
Fault pin still keeps low even if the fault events released

This sounds strange and shouldn't happen.

May I ask that with this testing process, did the TPA6304 back to PLAY mode? Which means, there would be PWM waveform form OUT pins, and the register 0xD and 0xE will show the channel into PLAY mode. Could you check the value in this two register?

0 Jingkun Wang 4 months ago in reply to Shadow He

Intellectual 295 points

Hello Shadow,

Sorry, I gave a wrong info.

Writing bit7 of 0x30 to clear fault, Fault pin changed to high
↓
Fault pin still keeps high even if the fault events kept.

Best Regards!

Wang Jingkun

0 Jingkun Wang 4 months ago in reply to Jingkun Wang

Intellectual 295 points

Add the waveform:

0 Shadow He 4 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

Jingkun Wang said:
Writing bit7 of 0x30 to clear fault, Fault pin changed to high
↓
Fault pin still keeps high even if the fault events kept.

This makes sense.

Because you already set Clear Fault, so the original OC fault already gone, device will think there's no fault and try to enter PLAY. But DC LDG function still takes effect, and stops the fault channel really PLAY.

And you also set the register to block DC LDG to pull low Fault pin. The Fault pin won't react, because there's no other fault, except for DC LDG fault.

0 Jingkun Wang 4 months ago in reply to Shadow He

Intellectual 295 points

Hi Shadow,

We hoped we can detect when the fault released.

Now the setting we can't detect the fault released.

If we didn't set the register to block DC LDG to pull down Fault pin.

The Fault pin will still keep changing from high to low. Because others channels can't pass the DC load.

So we don't know how to set to achieve the detection of fault happened and fault released.

Best Regards!

Wang Jingkun

0 Shadow He 4 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

For your using, it's indeed hard to only rely on Fault pin. It's a 4 channel device, not specially designed for 1 channel using. And suggest you to use together with the register information. All of the fault, and channel working state, will show up in the registers.

One possible way could still meet your target, but you need to follow the sequence closely, and make sure always keep un-used channel in Hi-Z, never set them into Mute or PLAY.

Pull low STBY pin, and power up device ->

Still keep STBY pin low, set register 0x5 with value 0x81 (to bypass power up load diag, so your un-used channel won't doing diag and report fault). ->

Now could pull up STBY pin, and wait 20ms as datasheet suggested. ->

If you still want to use load diag function, set the register 0x5 back to value 0x00 now. ->

Only set your used channel to PLAY, never set un-used channel to PLAY or Mute.

If you could follow this sequence closely, could avoid Load Diag function check your un-used channel, so no fault could be reported from them.

0 Jingkun Wang 4 months ago in reply to Shadow He

Intellectual 295 points

Hi `Shadow,

Now, we find another issue that "DVDD power on reset event" still be stored after reading.

We read the register 0x10 before standby changed from low to high.

But the event can't be cleared after reading.

Below is the configuration flow:

From datasheet, reading the I2C register(0x10 bit 4) clears the fault signaling bit.

But now we found that "DVDD power on reset event" still be stored after reading.

Could you have a check?

Best Regards!

Wang Jingkun

0 Shadow He 4 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

Have a try to only read this one register, don't do sequence/burst read.

0 Jingkun Wang 4 months ago in reply to Shadow He

Intellectual 295 points

Hi Shadow，

The result is same:

Best Regards!

Wang Jingkun

0 Shadow He 4 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

By closely looking into your log, I find the behavior is correct.

After pull up STBY, the first time you read 0x10 register, will have this POR report to you, to remind you re-power up happened. And that bit is cleared after you read it. The second time you read, it's already cleared.

0 Jingkun Wang 4 months ago in reply to Shadow He

Intellectual 295 points

Hi Shadow，

From the datasheet, the Fault pin can change from low to high before pulling up standby.

Now, our waveform seems that it must to set standby to high and read twice, the fault pin will pull up.

Could you check the reason?

Best Regards!

Wang Jingkun

0 Shadow He 4 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

I can't fully sure for now. For EVM testing, with STBY pin pull low and power up, surely the Fault pin won't go low, even the register 0x10 shows POR. Could you check your system, is the power supply all ready? And any specific register you changed?

0 Jingkun Wang 4 months ago in reply to Shadow He

Intellectual 295 points

Hi Shadow，

Could you provide the EVM's registers setting for us? I'll compare our setting.

Best Regards!

Wang Jingkun

0 Jingkun Wang 4 months ago in reply to Jingkun Wang

Intellectual 295 points

Hi Shadow,

Below is our configuration:

Could you check it?

Best Regards!

Wang Jingkun

0 Shadow He 3 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

It's the 1D register change, make the fault pin pull low. And there's description for the bit you set:

0 Jingkun Wang 3 months ago in reply to Shadow He

Intellectual 295 points

Hi Shadow,

Why can't the register be cleared after reading?

This register must be cleared after standby is pulled high and then read again.

If this register is not set, when the fault described by this register occurs, the Fault signal is invalid and the MCU cannot know that a fault has occurred.

Best Regards!

Wang Jingkun

0 Shadow He 3 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

Jingkun Wang said:
Why can't the register be cleared after reading?

This register must be cleared after standby is pulled high and then read again.

Before you pull up STBY pin, device will keep detect POR and report to you, it's no point try to clear before STBY pin.

Jingkun Wang said:
If this register is not set, when the fault described by this register occurs, the Fault signal is invalid and the MCU cannot know that a fault has occurred.

Not like that. When this fault is happening, device will surely detected and tell you with the Fault pin. Just the power fault is auto-recover by default. When the power back to normal, device will auto recover, and also auto-clear Fault pin.

That bit you set, is just to make all of power fault into Lached mode, Fault pin won't auto-recover, until you cleared the fault register.

Check register 0x10 and 0x11 for the difference.

0 Jingkun Wang 3 months ago in reply to Shadow He

Intellectual 295 points

Hi Shadow,

No matter how to set 0x1D bit3, the waveform of Fault and Standby is not consistent with the datasheet.

Could you check again above power up configuration?

Best Regards!

Wang Jingkun

0 Shadow He 3 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

As datasheet describes, happened at DVDD just set up moment.

0 Jingkun Wang 3 months ago in reply to Shadow He

Intellectual 295 points

Hi Shadow,

I know the DVDD POR happens at DVDD just set up.

I want to know why does the Fault signal be pulled high before standby is pulled high?

Now, no matter how to set 0x1D bit3, the waveform of Fault and Standby is not consistent with the datasheet.

Best Regards!

Wang Jingkun

0 Shadow He 3 months ago in reply to Jingkun Wang

TI__Mastermind 49430 points

Hi Jingkun

Jingkun Wang said:
I want to know why does the Fault signal be pulled high before standby is pulled high?

Because the Fault pin indeed not related with the STBY pin. Also not fully related with DVDD POR, if you not set the 0x1D bit3.

Below description indeed mentioned POR, but actually saying when DVDD crossing POR threshold, which means DVDD first time set up. Device will pull low Fault pin only 10ms time. Then will release the Fault pin. So if you find Fault pin always high, it is correct.

And this 10ms pull low time, is used for device to detect I2C address settings. Because the I2C address settings, also related with this pin, device will need to detect it when first time power up.

After device finished I2C address detection, will release Fault pin, and at this moment, your I2C is ready to use. The datasheet picture indeed drawing it, and not related with SBTY pin from below picture, right?