PCM6360-Q1: Communication abnormality

Hi, 

PCM6360 does not need an MCLK if operating in slave/target mode

To troubleshoot hardware, please verify the following: Ensure the power supply rails (AVDD,IOVDD,HVDD) are stable, power outputs (AREG,DREG) are stable, and the clocks are correct (FSYNC/BCLK). Your BCLK should be  #Ch * bit depth * sampling rate.. For example 6Ch * 32bit depth * 48kHz Fs = 9.216MHz BCLK.

Here an example script for TDM mode, 6 channel recording, 32bit depth, dc coupled mic input

# CHECKSUM 0
# -----------------------------------------------------------------------------
# Reset
# -----------------------------------------------------------------------------
# Select Page 0
w 90 00 00
# Reset Device
w 90 01 01
# 1mS Delay
# -----------------------------------------------------------------------------
# Begin Device Memory
# -----------------------------------------------------------------------------
# Page 0 (0x00) Dump
# Select Page 0
w 90 00 00
w 90 02 81
# Input Channel Enable
w 90 74 fc
# Power up/down
# Select page 0
w 90 00 00
w 90 75 a0

Hi,

Thanks. 

Our hardware platform adopts AC single ended mode， using 4ch，32bit，48k.

May I ask about the register timing of AC single ended mode. Also, if there is no waveform in the data, are there any debugging methods?

For example, which registers can be used to view the cause of the fault.

Hi,

Attached a modified script below. Typical errors are made through the troubleshooting tips i mentioned earlier, but you can also read register 0x15h to ensure the ASI bus is detecting the clock input correctly

# CHECKSUM 0
# -----------------------------------------------------------------------------
# Reset
# -----------------------------------------------------------------------------
# Select Page 0
w 90 00 00
# Reset Device
w 90 01 01
# 1mS Delay
# -----------------------------------------------------------------------------
# Begin Device Memory
# -----------------------------------------------------------------------------
# Page 0 (0x00) Dump
# Select Page 0
w 90 00 00
w 90 02 81
# Micbias Configuration
w 90 3b f0
# CH1 CFG, Gain, Volume, Gain cal, phase cal
w 90 3c a0
# CH2 CFG, Gain, Volume, Gain cal, phase cal
w 90 41 a0
# CH3 CFG, Gain, Volume, Gain cal, phase cal
w 90 46 b0
# CH4 CFG, Gain, Volume, Gain cal, phase cal
w 90 4b b0
# Input Channel Enable
w 90 73 f0
w 90 74 f0
# Power up/down
# Select page 0
w 90 00 00
w 90 75 80

If possible can you attach schematic?