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Original question:

TLV320AIC3110: Assistance with TLV320AIC3110IRHBR Audio Codec Configuration

TLV320AIC3110: Assistance Required: No Audio Output from TLV320AIC3110 on Custom Board

Samudra Jampani
Prodigy 55 points
Part Number: TLV320AIC3110

Tool/software:

Hi Sir,

We are working with the TLV320AIC3110 audio codec on our custom board. We are able to receive both MCLK and BCLK signals correctly. However, we are not getting any audio output.

The I²C configuration has been completed and verified to be correct. I have attached the relevant code and clock signal images for your reference.

Could you please help us identify the issue?

codecissue.zip

  • 0
    TI__Mastermind 46535 points

    Hi Samudra,

    Your WCLK is stuck high. The codec is expecting the WCLK from a host, like BCLK and MCLK yes? WCLK must also be provided by the host or else there will be no audio.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 55 points

    Dear Sir,

    We are able to get all the clocks. Please find the attached images for your reference.

    My new observation is that the SDI input is flat at zero, while the SDO output contains random traffic. The data does not belong to our application or the expected audio input. We are providing a sine wave as the audio input, but we are not getting any audio output from the speaker.

    Actually, we are performing pre-silicon validation, and the clocks are being provided by the FPGA with the help of RTL.4762.wclkmclkbclk.zip

    Best Regards,

    Samudralankaiah.

  • 0 in reply to Samudra Jampani
    TI__Mastermind 46535 points

    Hi Samudra,

    The analog and digital paths are independent, meaning the ADC and DAC path are not automatically linked. An analog sine wave provided at the input will be converted to digital and output on SDO. SDI input is given to the DAC and played out through the speaker. If SDI is flat at zero then there will be no output from the speaker.

    The clocks look good, but I see your frequencies are non-standard. Be sure to double check your clock tree settings that the math works out correctly and doesn't violate any limitations.

    This spreadsheet is a helpful tool to double check that your clock settings are passing all limitations: www.ti.com/.../01.00.00.00

    Best regards,
    Jeff McPherson